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Z9973

Document #: 38-07089 Rev. *D

Page 9 of 9

Document Title: Z9973 3.3V, 125 MHz Multi-Output Zero Delay Buffer
Document Number: 38-07089

Rev.

ECN No.

Issue Date

Orig. of

Change

Description of Change

107125

06/06/01

IKA

Convert from IMI to Cypress

108067

07/03/01

NDP

Changed Commercial to Industrial

111799

02/06/02

BRK

Convert from Word Doc to Adobe Framemaker Cypress Format
Changed the Timing Diagram and the operating voltage condition

116452

07/30/02

HWT

Corrected the Ordering Information to match the DevMaster.

122774

12/21/02

RBI

Add power up requirements to maximum ratings information.

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Содержание Z9973

Страница 1: ... 40x 1 0 0 0 4x 1 0 0 1 6x 1 0 1 0 8x 1 0 1 1 10x 1 1 0 0 8x 1 1 0 1 12x 1 1 1 0 16x 1 1 1 1 20x Block Diagram Pin Configuration REF_SEL 0 1 0 1 Phase Detector VCO LPF Sync Frz D Q QA0 Sync Frz D Q Sync Frz D Q Sync Frz D Q Sync Frz D Q Sync Frz D Q 0 1 2 Power On Reset Output Disable Circuitry Data Generator 4 6 8 12 4 6 8 10 2 4 6 8 4 6 8 10 Sync Pulse PECL_CLK PECL_CLK TCLK0 TCLK1 TCLK_SEL FB_I...

Страница 2: ...uts select the divide ratio at FB_OUT output See Table 1 52 VCO_SEL I PU VCO Divider Select Input When set LOW the VCO output is divided by 2 When set HIGH the divider is bypassed See Table 1 31 FB_IN I PU Feedback Clock Input Connect to FB_OUT for accessing the phase locked loop PLL 6 PLL_EN I PU PLL Enable Input When asserted HIGH PLL is enabled And when LOW PLL is bypassed 7 REF_SEL I PU Refere...

Страница 3: ...he propagation delay through the device is eliminated The PLL works to align the output edge with the input reference edge thus producing near zero delay The reference frequency affects the static phase offset of the PLL and thus the relative delay between inputs and outputs Because the static phase offset is a function of the reference clock the Tpd of the Z9973 is a function of the configuration...

Страница 4: ...nt 38 07089 Rev D Page 4 of 9 SYNC QC QA SYNC QC QA SYNC QA QC SYNC QC QA SYNC QA QC SYNC QC QA SYNC QC QA VCO 1 1 Mode 2 1 Mode 3 1 Mode 3 2 Mode 4 1 Mode 4 3 Mode 6 1 Mode Figure 1 Sync Output Waveforms Feedback ...

Страница 5: ...is frozen when a logic 0 is programmed and enabled when a logic 1 is written The enabling and freezing of individual outputs is done in such a manner as to eliminate the possibility of partial runt clocks The serial input register is programmed through the SDATA input by writing a logic 0 start bit followed by 12 NRZ freeze enable bits see Figure 2 The period of each SDATA bit equals the period of...

Страница 6: ...L_CLK 300 1000 mV VCMR Common Mode Range PECL_CLK 9 VDD 2 0 VDD 0 6 V IIL Input Low Current 10 120 µA IIH Input High Current 10 120 µA VOL Output Low Voltage 11 IOL 20 mA 0 5 V VOH Output High Voltage 11 IOH 20 mA 2 4 V IDDQ Quiescent Supply Current 10 15 mA IDDA PLL Supply Current VDD only 15 20 mA IDD Dynamic Supply Current QA and QB 60 MHz QC 120 MHz CL 30 pF 225 mA QA and QB 25 MHz QC 50 MHz C...

Страница 7: ... transmission lines Fout Maximum Output Frequency Q 2 125 MHz Q 4 120 Q 6 80 Q 8 60 FoutDC Output Duty Cycle 6 TCYCLE 2 750 TCYCLE 2 750 ps tpZL tpZH Output Enable Time 6 all outputs 2 10 ns tpLZ tpHZ Output Disable Time 6 all outputs 2 8 ns TCCJ Cycle to Cycle Jitter peak to peak 6 100 ps TSKEW Any Output to Any Output Skew 6 7 250 350 ps Propagation Delay 7 8 225 25 175 ps Tpd QFB 8 70 130 330 1...

Страница 8: ...not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress Semiconductor products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges Pac...

Страница 9: ...06 01 IKA Convert from IMI to Cypress A 108067 07 03 01 NDP Changed Commercial to Industrial B 111799 02 06 02 BRK Convert from Word Doc to Adobe Framemaker Cypress Format Changed the Timing Diagram and the operating voltage condition C 116452 07 30 02 HWT Corrected the Ordering Information to match the DevMaster D 122774 12 21 02 RBI Add power up requirements to maximum ratings information Feedba...

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