Cypress Semiconductor STK11C88 страница 7 Скачать руководство пользователя

Страница: 7 / 15

STK11C88

Document Number: 001-50591 Rev. **

Page 7 of 15

Capacitance

In the following table, the capacitance parameters are listed.

[4]

Parameter

Description

Test Conditions

Max

Unit

Input Capacitance

= 25

C, f = 1 MHz,

= 0 to 3.0 V

OUT

Output Capacitance

Thermal Resistance

In the following table, the thermal resistance parameters are listed.

[4]

Parameter

Description

Test Conditions

28-SOIC

(300 mil)

28-SOIC

(330 mil)

Unit

Thermal Resistance
(Junction to Ambient)

Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA / JESD51.

TBD

C/W

Thermal Resistance
(Junction to Case)

TBD

C/W

Figure 4. AC Test Loads

AC Test Conditions

5.0V

Output

30 pF

R1 480

255

Input Pulse Levels .................................................. 0 V to 3 V
Input Rise and Fall Times (10% - 90%)........................ <5 ns
Input and Output Timing Reference Levels ................... 1.5 V

Note

4. These parameters are guaranteed by design and are not tested.

[+] Feedback

Содержание STK11C88

Страница 1: ...in 300 mil and 330 mil SOIC packages RoHS compliance Functional Description The Cypress STK11C88 is a 256 Kb fast static RAM with a nonvolatile element in each memory cell The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides unlimited read and write cycles while independent nonvolatile data resides in the high...

Страница 2: ...put Write Enable Input Active LOW When the chip is enabled and WE is LOW data on the IO pins is written to the specific address location CE E Input Chip Enable Input Active LOW When LOW selects the chip When HIGH deselects the chip OE G Input Output Enable Active LOW The active LOW OE input enables the data output buffers during read cycles Deasserting OE HIGH causes the IO pins to tri state VSS G...

Страница 3: ...esses is used for STORE initiation it is important that no other READ or WRITE accesses intervene in the sequence If they intervene the sequence is aborted and no STORE or RECALL takes place To initiate the software STORE cycle the following READ sequence is performed 1 Read address 0x0E38 Valid READ 2 Read address 0x31C7 Valid READ 3 Read address 0x03E0 Valid READ 4 Read address 0x3C1F Valid READ...

Страница 4: ...TEs 4 CMOS versus TTL input levels 5 The operating temperature 6 The VCC level 7 IO loading Best Practices nvSRAM products have been used effectively for over 15 years While ease of use is one of the product s main system values the experience gained working with hundreds of appli cations has resulted in the following suggestions as best practices The nonvolatile cells in a nvSRAM are programmed o...

Страница 5: ...Output Data Output Data 1 2 L H 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F 0x0C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL Output Data Output Data Output Data Output Data Output Data Output Data 1 2 Notes 1 The six consecutive addresses must be in the order listed WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle 2 While there are 15 ...

Страница 6: ...mA mA ICC2 Average VCC Current during STORE All Inputs Do Not Care VCC Max Average current for duration tSTORE 3 mA ICC3 Average VCC Current at tRC 200 ns 5V 25 C Typical WE VCC 0 2V All other inputs cycling Dependent on output loading and cycle rate Values obtained without output loads 10 mA ISB1 3 Average VCC Current Standby Cycling TTL Input Levels tRC 25ns CE VIH tRC 45ns CE VIH Commercial 30 ...

Страница 7: ...rameter Description Test Conditions 28 SOIC 300 mil 28 SOIC 330 mil Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 TBD TBD C W ΘJC Thermal Resistance Junction to Case TBD TBD C W Figure 4 AC Test Loads AC Test Conditions 5 0V Output 30 pF R1 480Ω R2 255Ω Input Pulse Levels 0 V to 3 V Input R...

Страница 8: ...hip Disable to Output Inactive 10 15 ns tLZOE 7 tGLQX Output Enable to Output Active 0 0 ns tHZOE 7 tGHQZ Output Disable to Output Inactive 10 15 ns tPU 4 tELICCH Chip Enable to Power Active 0 0 ns tPD 4 tEHICCL Chip Disable to Power Standby 25 45 ns Switching Waveforms Figure 5 SRAM Read Cycle 1 Address Controlled 5 6 Figure 6 SRAM Read Cycle 2 CE and OE Controlled 5 W5 W W2 5 66 4 7 287 7 9 5 66...

Страница 9: ...tup to Start of Write 0 0 ns tHA tWHAX tEHAX Address Hold After End of Write 0 0 ns tHZWE 7 8 tWLQZ Write Enable to Output Disable 10 15 ns tLZWE 7 tWHQX Output Active After End of Write 5 5 ns Switching Waveforms Figure 7 SRAM Write Cycle 1 WE Controlled 9 Figure 8 SRAM Write Cycle 2 CE Controlled 9 tWC tSCE tHA tAW tSA tPWE tSD tHD tHZWE tLZWE ADDRESS CE WE DATA IN DATA OUT DATA VALID HIGH IMPED...

Страница 10: ...el 3 6 V VSWITCH Low Voltage Trigger Level 4 0 4 5 V Switching Waveforms Figure 9 STORE INHIBIT Power Up RECALL VCC VSWITCH VRESET POWER UP RECALL DQ DATA OUT STORE INHIBIT 5V tHRECALL POWER UP RECALL BROWN OUT STORE INHIBIT NO RECALL VCC DID NOT GO BELOW VRESET BROWN OUT STORE INHIBIT NO RECALL VCC DID NOT GO BELOW VRESET BROWN OUT STORE INHIBIT RECALL WHEN VCC RETURNS ABOVE VSWITCH Notes 10 tHRE...

Страница 11: ... tELAX Address Hold Time 20 20 ns tRECALL 11 RECALL Duration 20 20 μs Switching Waveforms Figure 10 CE Controlled Software STORE RECALL Cycle 12 tRC tRC tSA tSCE tHACE tSTORE tRECALL DATA VALID DATA VALID 6 S S E R D D A 1 S S E R D D A HIGH IMPEDANCE ADDRESS CE OE DQ DATA Notes 11 The software sequence is clocked on the falling edge of CE without involving OE double clocking abort the sequence 12...

Страница 12: ...Commercial STK11C88 NF45 51 85026 28 Pin SOIC 300 mil STK11C88 SF45TR 51 85058 28 Pin SOIC 330 mil STK11C88 SF45 51 85058 28 Pin SOIC 330 mil STK11C88 NF45ITR 51 85026 28 Pin SOIC 300 mil Industrial STK11C88 NF45I 51 85026 28 Pin SOIC 300 mil STK11C88 SF45ITR 51 85058 28 Pin SOIC 330 mil STK11C88 SF45I 51 85058 28 Pin SOIC 330 mil All parts are Pb free The above table contains Final information Co...

Страница 13: ...7 0 015 0 38 0 050 1 27 0 013 0 33 0 019 0 48 0 026 0 66 0 032 0 81 0 697 17 70 0 713 18 11 0 004 0 10 1 14 15 28 PART S28 3 STANDARD PKG SZ28 3 LEAD FREE PKG MIN MAX NOTE 1 JEDEC STD REF MO 119 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH BUT MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 010 in 0 254 mm PER SIDE 3 DIMENSIONS IN INCHES 4 PACKAGE WEIGHT 0 85gms DOES INCLUDE MOL...

Страница 14: ...STK11C88 Document Number 001 50591 Rev Page 14 of 15 Figure 12 28 Pin 330 mil SOIC 51 85058 Package Diagrams continued 51 85058 A Feedback ...

Страница 15: ...as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNE...

Результаты поиска

Содержание STK11C88

Отзывы:

Похожие инструкции для STK11C88

Бренды по названию

Популярные бренды

Cypress Semiconductor STK11C88, Техническое описание

Результаты поиска

Содержание STK11C88

Отзывы:

Похожие инструкции для STK11C88

Бренды по названию

Популярные бренды