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SL811HS

Document 38-08008 Rev. *D

Page 29 of 32

DMA Read Cycle

Note

Data is held until nDACK goes high regardless of state of nREAD.

Reset Timing

Note

Clock is 48 MHz nominal.

Parameter

Description

Min.

Typ.

Max.

tdack

nDACK low

100 ns

tddrdlo

nDACK to nRD low delay

0 ns

tdckdr

nDACK low to nDRQ high delay

5 ns

tdrdp

nRD pulse width

90 ns

tdhld

Date hold after nDACK high

5 ns

tddaccs

Data access from nDACK low

85 ns

tdrdack

nRD high to nDACK high

0 ns

tdakrq

nDRQ low after nDACK high

5 ns

trdcycle

DMA Read Cycle Time

150 ns

n D R Q

n D A C K

D 0-D 7

D A T A

n R D

S L 811 D M A R E A D C Y C L E T IM IN G

tdrdp

tdaccs

tdack

tdhld

tddrdlo

tdckdr

tdakrq

SL811 DMA Read Cycle Timing

nRST

treset

nRD or nWR

tioact

Reset Timing

Parameter

Description

Min.

Typ.

Max.

RESET

nRst Pulse width

16 clocks

IOACT

nRst HIGH to nRD or nWR active

16 clocks

Содержание SL811HS

Страница 1: ...ng in either full speed or low speed The SL811HS interfaces to devices such as microprocessors microcontrollers DSPs or directly to a variety of buses such as ISA PCMCIA and others The SL811HS USB Host Controller conforms to USB Specification 1 1 The SL811HS incorporates USB Serial Interface functionality along with internal full or low speed transceivers The SL811HS supports and operates in USB f...

Страница 2: ...rs and the remaining 240 bytes are used for USB data buffers When in slave mode peripheral mode the first 64 bytes are used for the four endpoint control and status registers along with the various other registers This leaves 192 bytes of endpoint buffer space for USB data transfers Access to the registers and data memory is through the 8 bit external microprocessor data bus in either indexed or d...

Страница 3: ...nded receivers Internally the trans ceiver interfaces to the Serial Interface Engine SIE logic Externally the transceiver connects to the physical layer of the USB SL811HS Registers Operation and control of the SL811HS is managed through internal registers When operating in Master Host mode the first 16 address locations are defined as register space In Slave Peripheral mode the first 64 bytes are...

Страница 4: ... or microcontroller when one of the USB protocol transac tions is completed Table 1 and Table 2 show the two sets of USB Host Control registers the A set and B set The two register sets allow for overlapping operation When one set of parameters is being set up the other is transferring On completion of a transfer to an endpoint the next operation is controlled by the other register set Note The US...

Страница 5: ...s to a low speed device via the HUB Set SL811HS SIE to operate at full speed i e bit 5 of register 05h Control Register 1 0 Set bit 6 of register 0Fh Control Register 2 0 Set correct polarity of DATA and DATA state for full speed Set bit 7 Preamble bit 1 in the Host Control register When SL811HS communicates directly to a low speed device Set bit 5 of register 05h Control Register 1 1 Set bit 6 of...

Страница 6: ...ion All 16 Endpoints can be addressed by the SL811HS PID 3 0 4 bit PID Field See Table Below EP 3 0 4 bit Endpoint Value in Binary Table 5 USB A USB B Host Base Length Definition Address 02h 0Ah Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HBL7 HBL6 HBL5 HBL4 HBL3 HBL2 HBL1 HBL0 Table 6 USB A USB B USB Packet Status Register Definition when READ Address 03h 0Bh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit...

Страница 7: ... DA6 DA0 Device address up to 127 devices can be addressed DA7 Reserved bit must be set to zero SL811HS Control Registers The next set of registers are the Control registers and control more of the operation of the chip instead of USB packet type of transfers Table 10 is a summary of the control registers Table 8 USB A USB B Host Transfer Count Register when READ Address 04h 0Ch Bit 7 Bit 6 Bit 5 ...

Страница 8: ...USB Reset Sequence After a device is detected write 08h to the Control register 05h to initiate the USB reset then wait for the USB reset time root hub should be 50 ms and additionally some types of devices such as a Forced J state Lastly set the Control register 05h back to 0h After the reset is complete the auto SOF generation is enabled SOF Packet Generation The SL811HS automatically computes t...

Страница 9: ... should not be written by the user in host mode Registers 08h 0Ch Host B registers Registers 08h 0Ch have the same definition as registers 00h 04h except they apply to Host B instead of Host A Table 13 Interrupt Enable Register Address 06h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved Device Detect Resume Inserted Removed SOF Timer Reserved Reserved USB B DONE USB A DONE Bit Position Bi...

Страница 10: ...below with bits 5 and 6 bit 7 is used to detect if the inserted device is low speed 0 or full speed 1 6 Device Detect Resume Device Detect Resume Interrupt Bit 6 is shared between Device Detection status and Resume Detection interrupt When bit 6 of register 05h is set to one this bit is the Resume detection Interrupt bit Otherwise this bit is used to indicate the presence of a device 1 device Not ...

Страница 11: ...gister set is used when SL811HS full feature bit is enabled Example To set up host to generate 1 ms SOF time The register 0Fh contains the upper 6 bits of the SOF timer Register 0Eh contains the lower 8 bits of the SOF timer The timer is based on an internal 12 MHz clock and uses a counter which counts down to zero from an initial value To set the timer for 1 ms time the register 0Eh is loaded wit...

Страница 12: ...SL811HS is ready for the next transfer without interruption Endpoints 0 3 Register Addresses Each endpoint set has a group of five registers that are mapped within the SL811HS memory The register sets have address assignments as shown in the following table For each endpoint set starting at address Index 0 the registers are mapped as shown in the following table Table 19 SL811HS Slave Peripheral M...

Страница 13: ... Arm Bit Position Bit Name Function 7 Reserved 6 Sequence Sequence bit 0 if DATA0 1 if DATA1 5 Send STALL When set to 1 sends Stall in response to next request on this endpoint 4 ISO When set to 1 allows Isochronous mode for this endpoint 3 Next Data Set 0 if next data set is A 1 if next data set is B 2 Direction When Direction 1 transmit to Host IN When Direction 0 receive from Host OUT 1 Enable ...

Страница 14: ...ection 5 3 1 The Control and Status registers are mapped as follows Table 25 Endpoint Packet Status Reg Address EP0a b 03h 0Bh EP1a b 13h 1Bh EP2a b 23h 2Bh EP3a b 33h 3Bh 7 6 5 4 3 2 1 0 Reserved Reserved Overflow Setup Sequence Time out Error ACK Bit Position Bit Name Function 7 Reserved Not applicable 6 Reserved Not applicable 5 Overflow Overflow condition maximum length exceeded during receive...

Страница 15: ...J K0 force state control bits are used to generate various USB bus conditions Forcing K state is used for Peripheral device remote wake up Resume and other modes These two bits are set to zero on power up see Table 29 for functions 3 J K0 2 DMA Dir DMA Transfer Direction Set equal to 1 for DMA READ cycles from SL811HS Set equal to 0 for DMA WRITE cycles 1 DMA Enable Enable DMA operation when equal...

Страница 16: ... has no effect on the status Table 30 Interrupt Enable Register Address 06h 7 6 5 4 3 2 1 0 DMA Status USB Reset SOF Received DMA Done Endpoint 3 Done Endpoint 2 Done Endpoint 1 Done Endpoint 0 Done Bit Position Bit Name Function 7 DMA Status When equal to 1 indicates DMA transfer is in progress When equal to 0 indicates DMA transfer is complete 6 USB Reset Enable USB Reset received interrupt when...

Страница 17: ...ween a peripheral to the SL811HS The count may sometimes require up to 16 bits therefore the count is repre sented in two registers Total Count Low and Total Count High EP3 is only supported with DMA operation DMA Total Count High Register Address 36h The DMA Total Count High register contains the high order 8 bits of DMA count When written this register enables DMA if the DMA Enable bit is set in...

Страница 18: ...11HST AXC 28 Pin PLCC Physical Connections 28 Pin PLCC Pin Layout See Table 35 on page 21 for Pin and Signal Description for Pins 2 and 3 in Host Mode 28 Pin PLCC Mechanical Dimensions 1 2 28 nDACK nDRQ nRD nWR D7 D6 D5 D4 Gnd D3 D2 D1 D0 Gnd INTRQ VDD1 nRST VDD2 Gnd nCS DATA DATA VDD1 CLK X1 X2 28 PLCC A0 M S 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 25 24 22 21 20 19 18 27 26 23 CM Figure 4 28 pin P...

Страница 19: ...llustrates a simple 3 3V voltage source Package Markings 28 pin PLCC YYWW Date code XXXX Product code X X Silicon revision number 5V USB GND R1 3 3 V VDD Sample VDD Generator 45 Ohms 3 9v 1N52288CT Zener 2N2222 Figure 5 Sample VDD Generator Part Number YYWW X X XXXX ...

Страница 20: ...Host Mode 48 Pin TQFP Mechanical Dimensions Note 4 NC Indicates No Connection NC Pins must be left unconnected 48 Pin TQFP 1 12 13 24 25 48 37 36 NC NC NC NC NC NC NC NC NC NC Data nRD NC NC NC NC NC nWR nCS CM VDD1 Data VDD Clk X1 X2 nRST INTRQ GND D0 D1 D2 D3 GND D4 D5 D6 D7 VDD M S A0 nDACK NC nDRQ USBGnd NC NC NC NC Figure 6 48 Pin TQFP AXC USB Host Slave Controller Pin Layout 4 ...

Страница 21: ...C NC No connection 14 NC NC No connection 15 7 12 VDD 3 3 VDC Device VDD Power 16 13 IN CLK X1 Clock or External Crystal X1 connection The X1 X2 Clock requires external 12 or 48 MHz matching crystal or clock source 17 14 OUT X2 External Crystal X2 connection 18 15 IN nRST Device active low reset input 19 16 OUT INTRQ Active HIGH Interrupt Request output to external controller 20 17 GND GND Device ...

Страница 22: ...ed HIGH logic 1 44 3 OUT nDRQ DMA Request An active LOW output used with an external DMA controller nDRQ and nDACK form the handshake for DMA data transfers In host mode leave the pin unconnected 45 4 IN nRD Read Strobe Input An active LOW input used with nCS to read registers data memory 46 NC NC No connection 47 NC NC No connection 48 NC NC No connection Table 35 48 28 Pin TQFP AXC Pin Assignmen...

Страница 23: ...SL811HS Document 38 08008 Rev D Page 23 of 32 Package Markings 48 Pin TQFP YYWW Date code XXXX Product code X X Silicon revision number Part Number YYWW X X XXXX ...

Страница 24: ...age VDD1 4 0V Lead Temperature 10 seconds 180 C Notes 10 The 28 PIN plcc can use a 12 MHz Crystal Oscillator or 12 MHz Clock Source 11 Fundamental mode for 12 MHz Crystal 12 The SL811HS can use a 12 MHz Clock Source Parameter Min Typical Max Power Supply Voltage VDD 3 0V 3 3V 3 45V Power Supply Voltage VDD1 3 0V 3 45V Operating Temperature 0 C 65 C Crystal Requirements X1 X2 Min Typical Max Operat...

Страница 25: ...c USB FS 21 mA 25 mA ICCsus1 14 Supply Current VDD Suspend w Clk Pll Enb 4 2 mA 5 mA ICCsus2 15 Supply Current VDD Suspend no Clk Pll Dis 50 μA 60 μA IUSB Supply Current VDD1 10 mA IUSBSUS Transceiver Supply Current in Suspend 10 μA Parameter Description Min Typ 16 Max VIHYS Differential Input Sensitivity Data Data 0 2V 200 mV VUSBIH USB Input Voltage HIGH Driven 2 0V VUSBIL USB Input Voltage LOW ...

Страница 26: ...hld I O Write Cycle to Register or Memory Buffer Register or Memory Address nCS twcsu twshld Tcscs See Note twrhigh Parameter Description Min Typ Max tWR Write pulse width 85 ns tWCSU Chip select set up to nWR LOW 0 ns tWSHLD Chip select hold time After nWR HIGH 0 ns tWASU A0 address set up time 85 ns tWAHLD A0 address hold time 10 ns tWDSU Data to Write HIGH set up time 85 ns tWDHLD Data hold tim...

Страница 27: ...u nCS tracc Tcscs Note twrrdl Parameter Description Min Typ Max tWR Write pulse width 85 ns tRD Read pulse width 85 ns tWCSU Chip select set up to nWR 0 ns tWASU A0 address set up time 85 ns tWAHLD A0 address hold time 10 ns tWDSU Data to Write HIGH set up time 85 ns tWDHLD Data hold time after Write HIGH 5 ns tRACC Data valid after Read LOW 25 ns 85 ns tRDHLD Data hold after Read HIGH 40 ns tRCSU...

Страница 28: ...p Max tdack nDACK low 80 ns tdwrlo nDACK to nWR low delay 5 ns tdakrq nDACK low to nDRQ high delay 5 ns tdwrp nWR pulse width 65 ns tdhld Data hold after nWR high 5 ns tdsu Data set up to nWR strobe low 60 ns tackrq NDACK high to nDRQ low 5 ns tackwrh NDACK high to nDRQ low 5 ns twrcycle DMA Write Cycle Time 150 ns nDRQ nDACK D0 D7 DATA nWR SL811 DMA WRITE CYCLE TIMING tdwrp tdsu tdack tdhld tdwrl...

Страница 29: ...s tdrdp nRD pulse width 90 ns tdhld Date hold after nDACK high 5 ns tddaccs Data access from nDACK low 85 ns tdrdack nRD high to nDACK high 0 ns tdakrq nDRQ low after nDACK high 5 ns trdcycle DMA Read Cycle Time 150 ns nDRQ nDACK D0 D7 DATA nRD SL811 DMA READ CYCLE TIMING tdrdp tdaccs tdack tdhld tddrdlo tdckdr tdakrq SL811 DMA Read Cycle Timing nRST treset nRD or nWR tioact Reset Timing Parameter...

Страница 30: ...ime 9 ns 11 ns tRISE Clock Rise Time 5 0 ns tFALL Clock Fall Time 5 0 ns Clock Duty Cycle 45 55 Part Number Package Type SL811HS 28 pin PLCC SL811HS JCT 28 pin Lead free SL811HST AXC 48 pin Lead free Package Diagrams DIMENSIONS IN INCHES MIN MAX 0 045 0 055 0 026 0 013 0 032 0 021 0 020 MIN 0 090 0 165 0 120 0 180 0 485 0 495 0 450 0 458 0 458 0 450 0 495 0 485 0 390 0 430 4 26 18 12 11 5 19 25 0 ...

Страница 31: ...press Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges ...

Страница 32: ...xample in section 5 3 9 13 Changed J K Programming States table in section 5 3 2 14 Added and removed comments for low power modes in section 5 3 4 15 Removed sections specific to slave operation and SL11H 16 Removed duplicate tables 17 General formatting changes to section headings 18 Fixed all part number references 19 Added comments to section 7 5 and new definitions to section 2 0 B 381894 See...

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