CY3270 PSoC® FirstTouch™ Kit Guide, Document No. 001-15945 Rev. *D
27
Hardware
Figure 4-10. CY8C21434 Master
Table 4-1. FTMF PSoC Pin Assignments
Pin Number
Port Number
Design Function
1
P0[1]
CapSense modulator capacitor
2
P2[7]
CapSense slider element 7
3
P2[5]
CapSense slider element 5
4
P2[3]
CapSense slider element 3
5
P2[1]
CapSense slider element 1
6
P3[3]
Unused / no-connect
7
P3[1]
CapSense feedback resistor
8
P1[7]
I2C clock line (SCL)
9
P1[5]
I2C data line (SDA)
10
P1[3]
Red LED drive
11
P1[1]
In system programming clock (ISSP_SCLK)
12
GND
13
P1[0]
In system programming data (ISSP_DAT)
14
P1[2]
Blue LED drive
15
P1[4]
Green LED drive
16
P1[6]
Alarm/buzzer FET drive
17
XRES
In system programming reset pin (ISSP_XRES)
18
P3[0]
Unused / no-connect
y
CSENSE5
CSENSE2
CSENSE7
CSENSE3
CSENSE4
CSENSE6
CSENSE1
ISSP_CLK
ISSP_XRES
ISSP_DAT
LED_BLUE
LED_GRN
I2C_SDA
I2C_SCL
TSENSE
PO2
PO4
PO5
LSENSE
ZVREF
PO3
ALARM
LED_RED
VEXP
VEXP
VEXP
0
6
03
R10
2.2K
TV2
PRX1
RECEPTACLE 1x1
1
1
U3
CY8C21434 MLF32
13
11
14
10
15
9
16
8
20
5
21
4
22
3
23
2
17
12
24
1
25
31
26
30
27
29
28
32
6
7
18
19
CP
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
XRES
VSS
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
VCC
VSS
P3_3
P3_1
P3_0
P3_2
CP
TV3
0
6
03
C1
0.01 uFd
0
6
03
R7
560
TV4
0
6
03
R9
2.2K
0
6
03
R5
2K
TV5