Cypress Semiconductor Perform CY7C1561V18 Скачать руководство пользователя страница 11

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CY7C1561V18, CY7C1576V18
CY7C1563V18, CY7C1565V18

Document Number: 001-05384 Rev. *F

Page 11 of 28

The write cycle description table for CY7C1576V18 follows.

[3, 11]

Write Cycle Descriptions

BWS

L–H

–

During the Data portion of a write sequence, the single byte (D

[8:0]

) is written into the device.

–

L–H

During the Data portion of a write sequence, the single byte (D

[8:0]

) is written into the device.

L–H

–

No data is written into the device during this portion of a write operation.

–

L–H

No data is written into the device during this portion of a write operation.

The write cycle description table for CY7C1565V18 follows.

[3, 11]

Write Cycle Descriptions

BWS

Comments

L–H

–

During the Data portion of a write sequence, all four bytes (D

[35:0]

) are written into

the device.

–

L–H During the Data portion of a write sequence, all four bytes (D

[35:0]

) are written into

the device.

L–H

–

During the Data portion of a write sequence, only the lower byte (D

[8:0]

) is written

into the device. D

[35:9]

remains unaltered.

–

L–H During the Data portion of a write sequence, only the lower byte (D

[8:0]

) is written

into the device. D

[35:9]

remains unaltered.

L–H

–

During the Data portion of a write sequence, only the byte (D

[17:9]

) is written into

the device. D

[8:0]

and D

[35:18]

remains unaltered.

–

L–H During the Data portion of a write sequence, only the byte (D

[17:9]

) is written into

the device. D

[8:0]

and D

[35:18]

remains unaltered.

L–H

–

During the Data portion of a write sequence, only the byte (D

[26:18]

) is written into

the device. D

[17:0]

and D

[35:27]

remains unaltered.

–

L–H During the Data portion of a write sequence, only the byte (D

[26:18]

) is written into

the device. D

[17:0]

and D

[35:27]

remains unaltered.

L–H

–

During the Data portion of a write sequence, only the byte (D

[35:27]

) is written into

the device. D

[26:0]

remains unaltered.

–

L–H During the Data portion of a write sequence, only the byte (D

[35:27]

) is written into

the device. D

[26:0]

remains unaltered.

L–H

–

No data is written into the device during this portion of a write operation.

–

L–H No data is written into the device during this portion of a write operation.

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Содержание Perform CY7C1561V18

Страница 1: ...ports the read port and the write port to access the memory array The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations QDR II architecture has separate data inputs and data outputs to completely eliminate the need to turn around the data bus that exists with common IO devices Each port is accessed through a com...

Страница 2: ...eg Reg 16 21 32 8 NWS 1 0 VREF Write Add Decode Write Reg 16 A 20 0 21 2M x 8 Array 2M x 8 Array 2M x 8 Array 8 CQ CQ DOFF Q 7 0 8 QVLD 8 8 8 Write Reg Write Reg Write Reg 2M x 9 Array CLK A 20 0 Gen K K Control Logic Address Register D 8 0 Read Add Decode Read Data Reg RPS WPS Control Logic Address Register Reg Reg Reg 18 21 36 9 BWS 0 VREF Write Add Decode Write Reg 18 A 20 0 21 2M x 9 Array 2M ...

Страница 3: ...18 BWS 1 0 VREF Write Add Decode Write Reg 36 A 19 0 20 1M x 18 Array 1M x 18 Array 1M x 18 Array 18 CQ CQ DOFF Q 17 0 18 QVLD 18 18 18 Write Reg Write Reg Write Reg 512K x 36 Array CLK A 18 0 Gen K K Control Logic Address Register D 35 0 Read Add Decode Read Data Reg RPS WPS Control Logic Address Register Reg Reg Reg 72 19 144 36 BWS 3 0 VREF Write Add Decode Write Reg 72 A 18 0 19 512K x 36 Arra...

Страница 4: ...SS VSS VSS VDDQ NC NC Q0 M NC NC NC VSS VSS VSS VSS VSS NC NC D0 N NC D7 NC VSS A A A VSS NC NC NC P NC NC Q7 A A QVLD A A NC NC NC R TDO TCK A A A NC A A A TMS TDI CY7C1576V18 8M x 9 1 2 3 4 5 6 7 8 9 10 11 A CQ A A WPS NC K NC 144M RPS A A CQ B NC NC NC A NC 288M K BWS0 A NC NC Q4 C NC NC NC VSS A NC A VSS NC NC D4 D NC D5 NC VSS VSS VSS VSS VSS NC NC NC E NC NC Q5 VDDQ VSS VSS VSS VDDQ NC D3 Q3...

Страница 5: ...NC D0 Q0 R TDO TCK A A A NC A A A TMS TDI CY7C1565V18 2M x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 288M A WPS BWS2 K BWS1 RPS A NC 144M CQ B Q27 Q18 D18 A BWS3 K BWS0 A D17 Q17 Q8 C D27 Q28 D19 VSS A NC A VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5 H...

Страница 6: ...ice is organized as 8M x 8 4 arrays each of 2M x 8 for CY7C1561V18 8M x 9 4 arrays each of 2M x 9 for CY7C1576V18 4M x 18 4 arrays each of 1M x 18 for CY7C1563V18 and 2M x 36 4 arrays each of 512K x 36 for CY7C1565V18 Therefore only 21 address inputs are needed to access the entire memory array of CY7C1561V18 and CY7C1576V18 20 address inputs for CY7C1563V18 and 19 address inputs for CY7C1565V18 T...

Страница 7: ...be connected to a pull up through a 10 KΩ or less pull up resistor The device behaves in QDR I mode when the DLL is turned off In this mode the device can be operated at a frequency of up to 167 MHz with QDR I timing TDO Output TDO for JTAG TCK Input TCK Pin for JTAG TDI Input TDI Pin for JTAG TMS Input TMS Pin for JTAG NC N A Not Connected to the Die Can be tied to any voltage level NC 144M N A N...

Страница 8: ...ng the next rising edge of the negative input clock K This enables for a seamless transition between devices without the insertion of wait states in a depth expanded memory Write Operations Write operations are initiated by asserting WPS active at the rising edge of the positive input clock K On the following K clock rise the data presented to D 17 0 is latched and stored into the lower 18 bit wri...

Страница 9: ...o the input clock of the QDR II The timing for the echo clocks are shown in Switching Characteristics on page 23 Valid Data Indicator QVLD QVLD is provided on the QDR II to simplify data capture on high speed systems The QVLD is generated by the QDR II device along with data output This signal is also edge aligned with the echo clock and follows the timing of any data pin This signal is asserted h...

Страница 10: ...e data portion of a write sequence CY7C1561V18 only the upper nibble D 7 4 is written into the device D 3 0 remains unaltered CY7C1563V18 only the upper byte D 17 9 is written into the device D 8 0 remains unaltered H L L H During the data portion of a write sequence CY7C1561V18 only the upper nibble D 7 4 is written into the device D 3 0 remains unaltered CY7C1563V18 only the upper byte D 17 9 is...

Страница 11: ...he device D 35 9 remains unaltered L H H H L H During the Data portion of a write sequence only the lower byte D 8 0 is written into the device D 35 9 remains unaltered H L H H L H During the Data portion of a write sequence only the byte D 17 9 is written into the device D 8 0 and D 35 18 remains unaltered H L H H L H During the Data portion of a write sequence only the byte D 17 9 is written int...

Страница 12: ... falling edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram on page 15 Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a res...

Страница 13: ...y scan register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation The shifting of data for the SAMPLE and P...

Страница 14: ... State Diagram TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 SELECT IR SCAN CAPTURE IR SHIFT IR EXIT1 IR PAUSE IR EXIT2 IR UPDATE IR Note 12 The 0 1 next to each state represents the value at TMS at the rising edge of TCK Feedback Feedback ...

Страница 15: ...H Voltage 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and Output Load Current GND VI VDD 5 5 μA 0 0 1 2 29 30 31 Boundary Scan Register Identification Register 0 1 2 108 0 1 2 Instruction Register Bypass Register Selection Circuitry Selection Circuitry TAP Controller TDI TDO TCK TMS Notes 13 These characteristics pertain to the TAP inputs TMS TCK TDI and TDO Parallel load levels...

Страница 16: ...TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions Figure 2 shows the TAP timing and test conditions 17 Figure 2 TAP Timing and Test Conditions tTL tTH a TDO CL 20 pF Z0 50Ω GND 0 9V 50Ω 1 8V 0V ALL INPUT PULSES 0 9V Test Clock Test Mode Select TCK TMS Test ...

Страница 17: ...ion Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operation SAMPLE Z 010 Captures the input and output contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESE...

Страница 18: ... 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43 11C 71 1D 99 2N 16 9N 44 9B 72 2C 100 2P 17 11L 45 10B 73 3E 101 1P 18 11M 46 11A 74 2D 102 3R 19 9L 47 10A 75 2E 103 4R 20 10L 48 9A 76 1E 104 4P 21 11K 49 8B 77 2F 105 5P 22 10K 50 7C 78 3F 106 ...

Страница 19: ...rovide stable power and clock K K for 2048 cycles to lock the DLL DLL Constraints DLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tKC Var The DLL functions at frequencies down to 120 MHz If the input clock is unstable and the DLL is enabled then the DLL may lock onto an incorrect frequency causing unstable SRAM behavior To avoid this provide 2...

Страница 20: ...VOH Output HIGH Voltage Note 19 VDDQ 2 0 12 VDDQ 2 0 12 V VOL Output LOW Voltage Note 20 VDDQ 2 0 12 VDDQ 2 0 12 V VOH LOW Output HIGH Voltage IOH 0 1 mA Nominal Impedance VDDQ 0 2 VDDQ V VOL LOW Output LOW Voltage IOL 0 1mA Nominal Impedance VSS 0 2 V VIH Input HIGH Voltage 14 VREF 0 1 VDDQ 0 15 V VIL Input LOW Voltage 14 0 15 VREF 0 1 V IX Input Leakage Current GND VI VDDQ 2 2 μA IOZ Output Leak...

Страница 21: ...0 ISB1 Automatic Power down Current Max VDD Both Ports Deselected VIN VIH or VIN VIL f fMAX 1 tCYC Inputs Static 400 MHz x8 550 mA x9 550 x18 550 x36 550 375 MHz x8 525 mA x9 525 x18 525 x36 525 333 MHz x8 500 mA x9 500 x18 500 x36 500 300 MHz x8 450 mA x9 450 x18 450 x36 450 Electrical Characteristics continued DC Electrical Characteristics Over the Operating Range 15 Parameter Description Test C...

Страница 22: ...meters Parameter Description Test Conditions 165 FBGA Package Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51 11 82 C W ΘJC Thermal Resistance Junction to Case 2 33 C W Figure 4 AC Test Loads and Waveforms 1 25V 0 25V R 50Ω 5 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES Device R...

Страница 23: ...h to Data Valid 0 2 0 2 0 2 0 2 ns tCQDOH tCQHQX Echo Clock High to Data Invalid 0 2 0 2 0 2 0 2 ns tCQH tCQHCQL Output Clock CQ CQ HIGH 26 0 81 0 88 1 03 1 15 ns tCQHCQH tCQHCQH CQ Clock Rise to CQ Clock Rise 26 rising edge to rising edge 0 81 0 88 1 03 1 15 ns tCHZ tCHQZ Clock K K Rise to High Z Active to High Z 26 27 0 45 0 45 0 45 0 45 ns tCLZ tCHQX1 Clock K K Rise to Low Z 26 27 0 45 0 45 0 4...

Страница 24: ... 4 5 6 7 8 CQ CQ Q tCQOH CCQO t CLZ t t CO tDOH tCQDOH CQD t tCHZ tCQOH CCQO t tQVLD QVLD QVLD DON T CARE UNDEFINED Read Latency 2 5 Cycles Q00 Q01 Q20 Q02 Q21 Q03 Q22 Q23 tCQH tCQHCQH Notes 31 Q00 refers to output from address A0 Q01 refers to output from the next internal burst address following A0 i e A0 1 32 Outputs are disabled High Z one clock cycle after a NOP 33 In this example if address ...

Страница 25: ...Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1576V18 400BZI CY7C1563V18 400BZI CY7C1565V18 400BZI CY7C1561V18 400BZXI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1576V18 400BZXI CY7C1563V18 400BZXI CY7C1565V18 400BZXI 375 CY7C1561V18 375BZC 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Commercial CY7C1576V18 375BZC CY7C1563V18 375BZC...

Страница 26: ...3BZXI 300 CY7C1561V18 300BZC 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Commercial CY7C1576V18 300BZC CY7C1563V18 300BZC CY7C1565V18 300BZC CY7C1561V18 300BZXC 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1576V18 300BZXC CY7C1563V18 300BZXC CY7C1565V18 300BZXC CY7C1561V18 300BZI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial...

Страница 27: ... CY7C1565V18 Document Number 001 05384 Rev F Page 27 of 28 Package Diagram Figure 6 165 ball FBGA 15 x 17 x 1 4 mm 51 85195 0 2 2 8 8 8 3 4 0 0 2 2 4 0 6 7 44 6 7 0 2 0 2 3 2 0 490 3 2 3 3 4 3 0 7 4 G 2 2 3 0 51 85195 A Feedback Feedback ...

Страница 28: ...described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems applicat...

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