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CY7C68000A

Document #: 38-08052 Rev. *G

Page 14 of 15

Quad Flat Package No Leads (QFN) Package

Design Notes

Electrical contact of the part to the Printed Circuit Board (PCB)

is made by soldering the leads on the bottom surface of the

package to the PCB. Hence, special attention is required to the

heat transfer area below the package to provide a good thermal

bond to the circuit board. A Copper (Cu) fill is to be designed into

the PCB as a thermal pad under the package. Heat is transferred

from the MoBL-USB TX2 through the device’s metal paddle on

the package bottom. From here, heat is conducted to the PCB at

the thermal pad. It is then conducted from the thermal pad to the

PCB inner ground plane by an array of via. A via is a plated

through-hole in the PCB with a finished diameter of 13 mil. The

QFN’s metal die paddle must be soldered to the PCB’s thermal

pad. Solder mask is placed on the board top, over each via, to

resist solder flow into the via. The mask on the top side also

minimizes outgassing during the solder reflow process.

For further information on this package design, refer to the appli-

cation note “Surface Mount Assembly of AMKOR’s MicroLead-

Frame (MLF) Technology.” Download this application note from

AMKOR’s website, by following this link:

http://www.amkor.com/products/notes_papers/MLFApp

Note.pdf

. The application note provides detailed information on

board mounting guidelines, soldering flow, and rework process.

Figure 8

displays a cross-sectional area under the package. The

cross section is of only one via. The solder paste template needs

to be designed to enable at least 50 percent solder coverage.

The thickness of the solder paste template should be 5 mil. It is

recommended that ‘No Clean’, type 3 solder paste be used for

mounting the part. Nitrogen purge is recommended during

reflow.

Figure 9

is a plot of the solder mask pattern image of the

assembly (darker areas indicate solder).

Figure 9. Plot of the Solder Mask (White Area)

Figure 8. Cross section of the Area Underneath the QFN Package

0.017” dia

Solder Mask

Cu Fill

PCB Material

0.013” dia

Via hole for thermally connecting the
QFN to the circuit board ground plane.

This figure only shows the top three layers of the
circuit board: Top Solder, PCB Dielectric, and
the Ground Plane

[+] Feedback

Содержание MoBL-USB CY7C68000A

Страница 1: ...the USB 2 0 Specification Supports transmission of Resume Signaling 3 3V Operation Two package options 56 pin QFN and 56 pin VFBGA All required terminations including 1 5 Kohm pull up on DPLUS are internal to chip Supports USB 2 0 Test Modes The Cypress MoBL USB TX2 is a Universal Serial Bus USB specification revision 2 0 transceiver serial and deserializer to a parallel interface of either 16 bit...

Страница 2: ...d IOs enabling the UTMI interface pins to be shared with other devices This is valuable in mobile handset applications where GPIOs are at a premium The outputs and IOs are tri stated 50ns when Tri state mode is enabled and are driven 50ns when Tri state mode is disabled All inputs must not be left floating while in Tri state mode When resuming after a suspend the PLL stabilizes approxi mately 200 ...

Страница 3: ...ates both the HS and FS transmitters and removes any termination from the USB making it appear to an upstream port that the device is disconnected from the bus Mode 2 disables Bit Stuff and NRZI encoding logic so 1 s loaded from the data bus becomes J s on the DPLUS DMINUS lines and 0 s become K s DPLUS DMINUS Impedance Termination The CY7C68000A does not require external resistors for USB data li...

Страница 4: ...V CC D2 Reserved D1 D0 CLK DataBus16_8 Uni_bidi GND TXValid V CC ValidH 28 27 26 25 24 23 22 21 20 19 18 17 16 15 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND D5 Reserved D6 D7 D8 D9 Reserved D10 D11 VCC D12 GND D13 TXReady Suspend Reset AVCC XTALOUT XTALIN AGND AVCC DPLUS DMINUS AGND XcvrSelect TermSelect OpMode0 V CC D14...

Страница 5: ...ure 2 CY7C68000A 56 pin VFBGA Pin Assignment 1 2 3 4 5 6 7 8 A B C D E F G H 1A 2A 3A 4A 5A 6A 7A 8A 1B 2B 3B 4B 5B 6B 7B 8B 1C 2C 3C 4C 5C 6C 7C 8C 1D 2D 7D 8D 1E 2E 7E 8E 1F 2F 3F 4F 5F 6F 7F 8F 1G 2G 3G 4G 5G 6G 7G 8G 1H 2H 3H 4H 5H 6H 7H 8H Feedback ...

Страница 6: ...nidirectional mode these bits are used as outputs for data selected by the TxValid signal 36 F3 D9 I O 34 F1 D10 I O 33 G4 D11 I O 31 E1 D12 I O 29 D8 D13 I O 27 G1 D14 I O 26 E2 D15 I O 50 A1 CLK Output Clock This output is used for clocking the receive and transmit parallel data on the D 15 0 bus 3 B2 Reset Input N A Active HIGH Reset Resets the entire chip This pin can be tied to VCC through a ...

Страница 7: ... Operational Mode These signals select among various operational modes 10 Description 00 0 Normal Operation 01 1 Non driving 10 2 Disable Bit Stuffing and NRZI encoding 11 3 Reserved 54 A5 TXValid Input Transmit Valid This signal indicates that the data bus is valid The asser tion of Transmit Valid initiates SYNC on the USB The negation of Trans mit Valid initiates EOP on the USB The start of SYNC...

Страница 8: ...led When Uni_Bidi 0 D 8 15 are un defined When Uni_Bidi 1 D 0 7 are valid on TxValid and D 8 15 are valid on RxValid CLK 60 MHz Note DataBus16_8 is static after Power on Reset POR and is only sampled at the end of Reset 6 H3 XTALIN Input N A Crystal Input Connect this signal to a 24 MHz parallel resonant funda mental mode crystal and 30 pF capacitor to GND It is also correct to drive XTALIN with a...

Страница 9: ...tics Table 2 DC Characteristics Parameter Description Conditions Min Typ Max Unit VCC Supply Voltage 3 0 3 3 3 6 V VIH Input High Voltage 2 5 25 V VIL Input Low Voltage 0 5 0 8 V II Input Leakage Current 0 VIN VCC 10 μA VOH Output Voltage High IOUT 4 mA 2 4 V VOL Output Low Voltage IOUT 4 mA 0 4 V IOH Output Current High 4 mA IOL Output Current Low 4 mA CIN Input Pin Capacitance Except DPLUS DMINU...

Страница 10: ...s Parameter Description Min Typ Max Unit Notes TCSU_MIN Minimum setup time for TXValid 4 ns TCH_MIN Minimum hold time for TXValid 1 ns TDSU_MIN Minimum setup time for Data transmit direction 4 ns TDH_MIN Minimum hold time for Data transmit direction 1 ns TCCO Clock to Control out time for TXReady RXValid RXActive and RXError 1 8 ns TCDO Clock to Data out time Receive direction 1 8 ns TCSU_MIN TCH_...

Страница 11: ... TDH_MIN Minimum hold time for Data Transmit direction 1 ns TCCO Clock to Control Out time for TXReady RXValid RXActive and RXError 1 20 ns TCDO Clock to Data out time Receive direction 1 20 ns TVSU_MIN Minimum setup time for ValidH transmit Direction 16 ns TVH_MIN Minimum hold time for ValidH Transmit direction 1 ns TCVO Clock to ValidH out time Receive direction 1 20 ns Parameter Description Min...

Страница 12: ... Package Type CY7C68000A 56LFXC 56 QFN CY7C68000A 56BAXC 56 VFBGA CY3683 MoBL USB TX2 Development Board Package Diagrams The MoBL USB TX2 is available in two packages 56 pin QFN 56 pin VFBGA Figure 6 56 Pin Quad Flatpack No Lead Package 8 x 8 mm Sawn Version LS56B 51 85187 C Feedback ...

Страница 13: ...Maintain a solid ground plane under the DPLUS and DMINUS traces Do not split the plane under these traces Do not place vias on the DPLUS or DMINUS trace routing Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm Package Diagrams continued Figure 7 56 VFBGA 5 x 5 x 1 0 mm 0 50 Pitch 0 30 Ball BZ56 TOP VIEW PIN A1 CORNER 0 50 3 50 5 00 0 10 BOTTOM VIEW 0 10 4X 3 5...

Страница 14: ...urther information on this package design refer to the appli cation note Surface Mount Assembly of AMKOR s MicroLead Frame MLF Technology Download this application note from AMKOR s website by following this link http www amkor com products notes_papers MLFApp Note pdf The application note provides detailed information on board mounting guidelines soldering flow and rework process Figure 8 display...

Страница 15: ...press Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any produc...

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