CY62148BN MoBL
®
Document #: 001-06517 Rev. *A
Page 4 of 10
Switching Characteristics
[5]
Over the Operating Range
Parameter
Description
62148BNLL-70
Unit
Min.
Max.
READ CYCLE
t
RC
Read Cycle Time
70
ns
t
AA
Address to Data Valid
70
ns
t
OHA
Data Hold from Address Change
10
ns
t
ACE
CE LOW to Data Valid
70
ns
t
DOE
OE LOW to Data Valid
35
ns
t
LZOE
OE LOW to Low Z
[6]
5
ns
t
HZOE
OE HIGH to High Z
[6, 7]
25
ns
t
LZCE
CE LOW to Low Z
[6]
10
ns
t
HZCE
CE HIGH to High Z
[6, 7]
25
ns
t
PU
CE LOW to Power-Up
0
ns
t
PD
CE HIGH to Power-Down
70
ns
WRITE CYCLE
[8]
t
WC
Write Cycle Time
70
ns
t
SCE
CE LOW to Write End
60
ns
t
AW
Address Set-Up to Write End
60
ns
t
HA
Address Hold from Write End
0
ns
t
SA
Address Set-Up to Write Start
0
ns
t
PWE
WE Pulse Width
55
ns
t
SD
Data Set-Up to Write End
30
ns
t
HD
Data Hold from Write End
0
ns
t
LZWE
WE HIGH to Low Z
[6]
5
ns
t
HZWE
WE LOW to High Z
[6, 7]
25
ns
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 100-pF load capacitance.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of
any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
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