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CY7C6431x

CY7C64345, CY7C6435x

enCoRe™ V Full Speed USB Controller

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Document Number: 001-12394 Rev *G

Revised January 30, 2009

Features

■

Powerful Harvard Architecture Processor

❐

M8C processor speeds running up to 24 MHz

❐

Low power at high processing speeds

❐

Interrupt controller

❐

3.0V to 5.5V operating voltage without USB

❐

Operating voltage with USB enabled:
• 3.15 to 3.45V when supply voltage is around 3.3V
• 4.35 to 5.25V when supply voltage is around 5.0V

❐

Temperature range: 0°C to 70°C

■

Flexible On-Chip Memory

❐

Up to 32K Flash program storage
• 50,000 erase and write cycles
• Flexible protection modes

❐

Up to 2048 bytes SRAM data storage

❐

In-System Serial Programming (ISSP)

■

Complete Development Tools

❐

Free development tool (PSoC Designer™)

❐

Full featured, in-circuit emulator and programmer

❐

Full speed emulation

❐

Complex breakpoint structure

❐

128K trace memory

■

Precision, Programmable Clocking

❐

Crystal-less oscillator with support for an external crystal or
resonator

❐

Internal ±5.0% 6, 12, or 24 MHz main oscillator
• 0.25% accuracy with Oscillator Lock to USB data, no

external components required

• Internal low speed oscillator at 32 kHz for watchdog and

sleep. The frequency range is 19 to 50 kHz with a 32 kHz
typical value

■

Programmable Pin Configurations

❐

25 mA sink current on all GPIO

❐

Pull Up, High Z, Open Drain, CMOS drive modes on all GPIO

❐

Configurable inputs on all GPIO

❐

Low dropout voltage regulator for Port 1 pins. Programmable
to output 3.0, 2.5, or 1.8V at the I/O pins

❐

Selectable, regulated digital I/O on Port 1
• Configurable input threshold for Port 1
• 3.0V, 20 mA total Port 1 source current
• Hot-swappable

❐

5 mA strong drive mode on Ports 0 and 1

■

Full-Speed USB (12 Mbps)

❐

Eight unidirectional endpoints

❐

One bidirectional control endpoint

❐

USB 2.0 compliant

❐

Dedicated 512 bytes buffer

❐

No external crystal required

■

Additional System Resources

❐

Configurable communication speeds

❐

C slave

• Selectable to 50 kHz, 100 kHz, or 400 kHz

• Implementation requires no clock stretching
• Implementation during sleep modes with less than 100

• Hardware address detection

❐

SPI master and SPI slave
• Configurable between 93.75 kHz and 12 MHz

❐

Three 16-bit timers

❐

8-bit ADC used to monitor battery voltage or other signals -
with external components

❐

Watchdog and sleep timers

❐

Integrated supervisory circuit

System Bus

6/12/24 MHz Internal Main Oscillator

CPU Core

(M8C)

SROM

Flash 32K

SYSTEM RESOURCES

I2C Slave/SPI

Master-Slave

POR and LVD

System Resets

Port 1

Port 0

Sleep and

Watchdog

Full

Speed

USB

Port 3

Port 2

Prog. LDO

SRAM

2048 Bytes

Interrupt

Controller

enCoRe V
CORE

3 16-Bit

Timers

Port 4

enCoRe V Block Diagram

[+] Feedback

Содержание enCoRe V CY7C6431x

Страница 1: ...range is 19 to 50 kHz with a 32 kHz typical value Programmable Pin Configurations 25 mA sink current on all GPIO Pull Up High Z Open Drain CMOS drive modes on all GPIO Configurable inputs on all GPIO...

Страница 2: ...wires SPI communication over three or four wires runs at speeds of 46 9 kHz to 3 MHz lower for a slower system clock In I2 C slave mode the hardware address recognition feature reduces the already lo...

Страница 3: ...mlessly within the PSoC Designer interface and have been tested with a full range of debugging tools The choice is yours Assemblers The assemblers allow assembly code to be merged seamlessly with C co...

Страница 4: ...each other with valuator functions In the chip level view you perform the selection configuration and routing so that you have complete control over the use of all on chip resources Generate Verify a...

Страница 5: ...e h for example 14h or 3Ah Hexadecimal numbers may also be represented by a 0x prefix the C coding convention Binary numbers have an appended lowercase b for example 01010100b or 01000011b Numbers not...

Страница 6: ...ng ISSP pins that are not High Z at power on reset POR Table 1 16 Pin Part Pinout QFN Pin No Type Name Description 1 I O P2 3 Digital I O Crystal Input Xin 2 IOHR P1 7 Digital I O SPI SS I2C SCL 3 IOH...

Страница 7: ...Digital I O SPI CLK 8 IOHR P1 1 1 2 Digital I O ISSP CLK I2C SCL SPI MOSI 9 Power Vss Ground 10 I O D USB PHY 11 I O D USB PHY 12 Power Vdd Supply voltage 13 IOHR P1 0 1 2 Digital I O ISSP DATA I2C SD...

Страница 8: ...Description 1 NC NC No connection 2 I O P2 7 Digital I O 3 I O P2 5 Digital I O Crystal Out Xout 4 I O P2 3 Digital I O Crystal In Xin 5 I O P2 1 Digital I O 6 I O P4 3 Digital I O 7 I O P4 1 Digital...

Страница 9: ...I O P2 2 Digital I O 35 I O P2 4 Digital I O 36 I O P2 6 Digital I O 37 IOH P0 0 Digital I O 38 IOH P0 2 Digital I O 39 IOH P0 4 Digital I O 40 IOH P0 6 Digital I O 41 Power Vdd Supply voltage 42 NC...

Страница 10: ...e has a total register address space of 512 bytes The register space is also referred to as IO space and is broken into two parts Bank 0 user space and Bank 1 configu ration space The XIO bit in the F...

Страница 11: ...DR 5A RW 9A INT_CLR0 DA RW 1B PMA3_DR 5B RW 9B INT_CLR1 DB RW 1C PMA4_DR 5C RW 9C INT_CLR2 DC RW 1D PMA5_DR 5D RW 9D INT_CLR3 DD RW 1E PMA6_DR 5E RW 9E INT_MSK2 DE RW 1F PMA7_DR 5F RW 9F INT_MSK1 DF R...

Страница 12: ..._CR0 54 94 D4 15 EP2_CR0 55 95 D5 16 EP3_CR0 56 96 D6 17 EP4_CR0 57 97 D7 18 EP5_CR0 58 98 D8 19 EP6_CRO 59 99 D9 1A EP7_CR0 5A 9A DA 1B EP8_CR0 5B 9B DB 1C 5C 9C IO_CFG DC RW 1D 5D 9D OUT_P1 DD RW 1E...

Страница 13: ...ency Vdd Voltage 3 0V 3 MHz V a l i d O p e r a t i n g R e g i o n 5 5V 750 kHz 6 MHz 24 MHz IMO Frequency Vdd Voltage 3 MHz 3 0V SLIMO Mode 01 12 MHz SLIMO Mode 00 SLIMO Mode 10 Table 7 Units of Mea...

Страница 14: ...ock DC Accuracy DNL 1 2 LSb For any configuration INL 2 2 LSb For any configuration Offset Error 0 15 90 mV Operating Current 275 350 A Data Clock 2 25 12 MHz Source is chip s internal main oscil lato...

Страница 15: ...specific See Package Handling on page 25 The user must limit the power consumption to comply with this requirement Table 9 DC Chip Level Specifications Parameter Description Conditions Min Typ Max Un...

Страница 16: ...IOH 10 A Vdd 3 0V maximum of 10 mA source current in all I Os Vdd 0 2 V VOH2 High Output Voltage Port 0 2 or 3 Pins IOH 1 mA Vdd 3 0 maximum of 20 mA source current in all I Os Vdd 0 9 V VOH3 High Ou...

Страница 17: ...ysteresis Voltage 50 60 200 mV IIL Input Leakage Absolute Value 0 001 1 A CPIN Pin Capacitance Package and pin dependent Temp 25o C 0 5 1 7 5 pF Table 12 DC POR and LVD Specifications Symbol Descripti...

Страница 18: ...ing Programming or Verify 8 1 5 mA VOLV Output Low Voltage During Programming or Verify Vss 0 75 V VOHV Output High Voltage During Programming or Verify Vdd 0 9 Vdd V FlashENPB Flash Write Endurance 9...

Страница 19: ...jitter To next transition 3 5 3 5 ns Tudj2 Driver differential jitter To pair transition 4 0 4 0 ns Tfdeop Source jitter for differential transition To SE0 transition 2 5 ns Tfeopt Source SE0 interva...

Страница 20: ...AC GPIO Specifications Symbol Description Conditions Min Typ Max Units FGPIO GPIO Operating Frequency Normal Strong Mode Ports 0 1 0 12 MHz TRise23 Rise Time Strong Mode Ports 2 3 Vdd 3 3 to 5 5V 10...

Страница 21: ...ns TFSCLK Fall Time of SCLK 1 20 ns TSSCLK Data Setup Time to Falling Edge of SCLK 40 ns THSCLK Data Hold Time from Falling Edge of SCLK 40 ns FSCLK Frequency of SCLK 0 8 MHz TERASEB Flash Erase Time...

Страница 22: ...Repeated START Condition 4 7 0 6 s THDDATI2C Data Hold Time 0 0 s TSUDATI2C Data Setup Time 250 100 15 ns TSUSTOI2C Setup Time for STOP Condition 4 0 0 6 s TBUFI2C Bus Free Time Between a STOP and ST...

Страница 23: ...enCoRe V USB device along with the thermal impedances for each package Important Note Emulation tools may require a larger area on the target PCB than the chip s footprint For a detailed description...

Страница 24: ...CY7C6431x CY7C64345 CY7C6435x Document Number 001 12394 Rev G Page 24 of 28 Figure 10 32 Pin 5 x 5 x 0 55 mm QFN 001 42168 C Feedback...

Страница 25: ...ory A label on the package has details about the actual bake temperature and the minimum bake time to remove this moisture The maximum bake time is the aggregate time that the parts exposed to the bak...

Страница 26: ...C64316 16LKXCT 16 Pin QFN Tape and Reel 3x3 mm 32K 2K 11 Hi end FS USB dongle RC host module CY7C64343 32LQXC 32 Pin QFN 3x3 mm 8K 1K 25 Full speed USB mouse CY7C64343 32LQXCT 32 Pin QFN 3X3 mm 8K 1K...

Страница 27: ...ap tables Corrected a value in the DC Chip Level Specifications table C 1241024 TYJ ARI See ECN Corrected Idd values in Table 6 DC Chip Level Specifications D 1639963 AESA See ECN Post to www cypress...

Страница 28: ...e used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except...

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