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CY7C64215

enCoRe™ III Full Speed USB Controller

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Document 38-08036 Rev. *C

Revised December 08, 2008

Features

■

Powerful Harvard Architecture Processor

❐

M8C Processor Speeds to 24 MHz

❐

Two 8x8 Multiply, 32-bit Accumulate

❐

3.0V to 5.25V Operating Voltage

❐

USB 2.0 USB-IF certified. TID# 40000110

❐

Operating Temperature Range: 0°C to +70°C

■

Advanced Peripherals (enCoRe™ III Blocks)

❐

6 Analog enCoRe III Blocks provide:
• Up to 14-bit Incremental and Delta-Sigma ADCs

❐

Programmable Threshold Comparator

❐

4 Digital enCoRe III Blocks provide:
• 8-bit and 16-bit PWMs, timers and counters
• I

C Master

• SPI Master or Slave
• Full Duplex UART
• CYFISNP and CYFISPI modules to talk to Cypress CYFI

radio

■

Complex Peripherals by Combining Blocks

■

Full-Speed USB (12 Mbps)

❐

Four Unidirectional Endpoints

❐

One Bidirectional Control Endpoint

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Dedicated 256 Byte Buffer

❐

No External Crystal Required

❐

Operational at 3.0V – 3.6V or 4.35V – 5.25V

■

Flexible On-Chip Memory

❐

16K Flash Program Storage 50,000 Erase/Write Cycles

❐

1K SRAM Data Storage

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In-System Serial Programming (ISSP)

❐

Partial Flash Updates

❐

Flexible Protection Modes

❐

EEPROM Emulation in Flash

■

Programmable Pin Configurations

❐

25-mA Sink on all GPIO

❐

Pull up, Pull down, High- Z, Strong, or Open Drain Drive
Modes on all GPIO

❐

Configurable Interrupt on all GPIO

■

Precision, Programmable Clocking

❐

Internal ±4% 24 and 48 MHz Oscillator

❐

Internal Oscillator for Watchdog and Sleep

❐

0.25% Accuracy for USB with no External Components

■

Additional System Resources

❐

™

Slave, Master, and Multi-Master to 400 kHz

❐

Watchdog and Sleep Timers

❐

User-Configurable Low Voltage Detection

❐

Integrated Supervisory Circuit

❐

On-Chip Precision Voltage Reference

■

Complete Development Tools

❐

Free Development Software (PSoC

Designer

™

)

❐

Full-Featured, In-Circuit Emulator and Programmer

❐

Full Speed Emulation

❐

Complex Breakpoint Structure

❐

128K Bytes Trace Memory

enCoRe III Core

Block Diagram

[+] Feedback

Содержание enCoRe III CY7C64215

Страница 1: ...point Dedicated 256 Byte Buffer No External Crystal Required Operational at 3 0V 3 6V or 4 35V 5 25V Flexible On Chip Memory 16K Flash Program Storage 50 000 Erase Write Cycles 1K SRAM Data Storage In...

Страница 2: ...levels on blocks of 64 bytes allowing customized software IP protection enCoRe III incorporates flexible internal clock generators including a 24 MHz IMO internal main oscillator accurate to 8 over te...

Страница 3: ...umulate to assist in both general math and digital filters The decimator provides a custom hardware filter for digital signal processing applications including the creation of Delta Sigma ADCs Digital...

Страница 4: ...el C language compiler developed specifically for the devices in the family Figure 3 PSoC Designer Subsystems PSoC Designer Software Subsystems Device Editor The Device Editor subsystem allows the use...

Страница 5: ...w cost high functionality ICE Cube is available for devel opment support This hardware has the capability to program single devices The emulator consists of a base unit that connects to the PC by way...

Страница 6: ...esigner to generate source code that automati cally configures the device to your specification and provides the high level user module API functions Figure 4 User Module and Source Code Development F...

Страница 7: ...1b Numbers not indicated by an h or b are decimal Acronym Description AC alternating current ADC analog to digital converter API application programming interface CPU central processing unit CT contin...

Страница 8: ...column output 34 IO M P3 2 47 IO I M P0 4 Analog column mux input and column output 35 IO M P3 4 48 IO I M P0 6 Analog column mux input 36 IO M P3 6 49 Power Vdd Supply voltage 37 IO M P4 0 50 Power V...

Страница 9: ...A 11 IO M P1 3 12 IO M P1 1 I2C Serial Clock SCL ISSP SCLK 13 Power GND Ground connection 14 USB D 15 USB D 16 Power Vdd Supply voltage 17 IO M P1 0 I2C Serial Data SDA ISSP SDATA 18 IO M P1 2 19 IO M...

Страница 10: ...o as IO space and is divided into two banks The XOI bit in the Flag register CPU_F determines which bank the user is currently in When the XOI bit is set the user is in Bank 1 Note In the following re...

Страница 11: ..._MSCR D9 1A EP0_DR2 5A RW 9A INT_CLR0 DA RW 1B EP0_DR3 5B RW 9B INT_CLR1 DB RW PRT7DR 1C RW EP0_DR4 5C RW 9C INT_CLR2 DC RW PRT7IE 1D RW EP0_DR5 5D RW 9D INT_CLR3 DD RW PRT7GS 1E RW EP0_DR6 5E RW 9E I...

Страница 12: ...2 96 RW D6 PRT5IC1 17 RW PMA7_RA 57 RW ASC21CR3 97 RW D7 18 58 98 MUX_CR0 D8 RW 19 59 99 MUX_CR1 D9 RW 1A 5A 9A MUX_CR2 DA RW 1B 5B 9B MUX_CR3 DB RW PRT7DM0 1C RW 5C 9C DC PRT7DM1 1D RW 5D 9D OSC_GO_E...

Страница 13: ...e used in this section Table 5 Units of Measure Symbol Unit of Measure Symbol Unit of Measure C degree Celsius W microwatts dB decibels mA milliampere fF femto farad ms millisecond Hz hertz mV millivo...

Страница 14: ...ply Voltage on Vdd Relative to Vss 0 5 6 0 V VIO DC Input Voltage Vss 0 5 Vdd 0 5 V VIO2 DC Voltage Applied to Tri state Vss 0 5 Vdd 0 5 V IMIO Maximum Current into any Port Pin 25 50 mA IMAIO Maximum...

Страница 15: ...0 367 kHz analog power off ISB Sleep Mode Current with POR LVD Sleep Timer and WDT 2 3 6 5 A Conditions are with internal slow speed oscil lator Vdd 3 3V 0 C TA 55 C analog power off ISBH Sleep Mode...

Страница 16: ...State Data Line Leakage 10 10 A 0V VIN 3 3V REXT External USB Series Resistor 23 25 In series with each USB pin VUOH Static Output High Driven 2 8 3 6 V 15 k 5 to Ground Internal pull up enabled VUOHI...

Страница 17: ...ion Min Typ Max Unit BG Bandgap Voltage Reference 1 28 1 30 1 32 V AGND Vdd 2 3 Vdd 2 0 04 Vdd 2 0 01 Vdd 2 0 007 V AGND 2 x BandGap 3 2 x BG 0 048 2 x BG 0 030 2 x BG 0 024 V AGND P2 4 P2 4 Vdd 2 3 P...

Страница 18: ...05 BG 0 015 V AGND 1 6 x BandGap 3 1 6 x BG 0 027 1 6 x BG 0 010 1 6 x BG 0 018 V AGND Column to Column Variation AGND Vdd 2 3 0 034 0 000 0 034 V RefHi Vdd 2 BandGap Not Allowed RefHi 3 x BandGap Not...

Страница 19: ...s VPPOR0R VPPOR1R VPPOR2R Vdd Value for PPOR Trip positive ramp PORLEV 1 0 00b PORLEV 1 0 01b PORLEV 1 0 10b 2 91 4 39 4 55 V V V VPPOR0 VPPOR1 VPPOR2 Vdd Value for PPOR Trip negative ramp PORLEV 1 0...

Страница 20: ...ming or Verify 1 5 mA Driving internal pull down resistor VOLV Output Low Voltage During Programming or Verify Vss 0 75 V VOHV Output High Voltage During Programming or Verify Vdd 1 0 Vdd V FlashENPB...

Страница 21: ...Hz 0 C TA 70 C FCPU1 CPU Frequency 5V Nominal 0 93 24 24 96 7 8 MHz FCPU2 CPU Frequency 3 3V Nominal 0 93 12 12 96 8 9 MHz FBLK5 Digital PSoC Block Frequency 5V Nominal 0 48 49 92 7 8 10 MHz Refer to...

Страница 22: ...re for design guidance only Table 19 AC GPIO Specifications Parameter Description Min Typ Max Unit Notes FGPIO GPIO Operating Frequency 0 12 MHz Normal Strong Mode TRiseF Rise Time Normal Strong Mode...

Страница 23: ...Frequency No Enable Input 49 92 MHz 4 75V Vdd 5 25V Maximum Frequency Enable Input 25 92 MHz Dead Band Kill Pulse Width Asynchronous Restart Mode 20 ns Synchronous Restart Mode 50 11 ns Disable Mode 5...

Страница 24: ...alling Slew Rate 80 to 20 1V Step 100 pF Load Power Low Power High 0 65 0 65 V s V s BWOBSS Small Signal Bandwidth 20mVpp 3 dB BW 100 pF Load Power Low Power High 0 8 0 8 MHz MHz BWOBLS Large Signal B...

Страница 25: ...Vdd 3 6 TDSCLK3 Data Out Delay from Falling Edge of SCLK 50 ns 3 0 Vdd 3 6 Table 26 AC Characteristics of the I2 C SDA and SCL Pins for Vdd Parameter Description Standard Mode Fast Mode Unit Notes Min...

Страница 26: ...08036 Rev C Page 26 of 30 Figure 8 Definition for Timing for Fast Standard Mode on the I2 C Bus SDA SCL S Sr S P TBUFI2C TSPI2C THDSTAI2C TSUSTOI2C TSUSTAI2C TLOWI2C THIGHI2C THDDATI2C THDSTAI2C TSUDA...

Страница 27: ...thermal impedance for the package Important Note Emulation tools may require a larger area on the target PCB than the chip s footprint For a detailed description of the emulation tools dimensions refe...

Страница 28: ...Package Package Typical JA 56 Pin MLF 20 oC W 28 Pin SSOP 96 o C W TJ TA POWER x JA 51 85079 C Table 28 Solder Reflow Peak Temperature Package Minimum Peak Temperature Maximum Peak Temperature 56 Pin...

Страница 29: ...erature and the minimum bake time to remove this moisture The maximum bake time is the aggregate time that the parts are exposed to the bake temperature Exceeding this exposure time may degrade device...

Страница 30: ...ress written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILI...

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