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CY7C601xx, CY7C602xx

Document 38-16016 Rev. *E

Page 23 of 68

Figure 12-1.  CPU Clock Block Diagram

SCALE

(divide by 2

n, 

n = 0-5,7)

MUX

CLK_EXT

CLK_24MHz

CPUCLK

SEL

CLK_CPU

Doubler

CLK_HS

LP OSC

32-KHz

CLK_32KHz

XTAL OSC

1-24MHz

CY7C601xx only

MUX

Crystal Oscillator Disabled

XOSC

SEL

EN

CLK_EXT

EFTB

P0.0

CLKIN

P0.1

CLKOUT

CY7C601xx

 only

Table 12-2.  CPU Clock Configuration (CPUCLKCR) [0x30] [R/W] 

Bit #

7

6

5

4

3

2

1

0

Field

Reserved

CPUCLK Select

Read/Write

–

–

–

–

–

–

–

R/W

Default

0

0

0

0

0

0

0

0

Bit [7:1]:

 Reserved

Bit 0:

 CPU CLK Select

0 = Internal 24 MHz Oscillator
1 = External oscillator source

Note

 The CPU speed selection is configured using the OSC_CR0 Register (

Table 12-3

).

Table 12-3.  OSC Control 0 (OSC_CR0) [0x1E0] [R/W] 

Bit #

7

6

5

4

3

2

1

0

Field

Reserved

No Buzz

Sleep Timer [1:0]

CPU Speed [2:0]

[+] Feedback 

[+] Feedback 

Содержание enCoRe CY7C601 Series

Страница 1: ...ns SPI serial communication Master or slave operation Configurable up to 2 Mbit per second transfers Supports half duplex single data line mode for optical sensors 2 channel 8 bit or 1 channel 16 bit...

Страница 2: ...plied to the device resets the logic to a known state and executes instructions at Flash address 0x0000 When power falls below a programmable trip voltage it generates a reset or is configured to gene...

Страница 3: ...22 23 24 26 25 VDD P2 7 P2 6 P2 5 P2 4 P0 7 INT2 P0 4 INT0 P0 2 P3 6 P1 6 SMISO P3 4 P1 7 P1 4 SCLK P1 5 SMOSI P1 3 SSEL P1 2 18 P3 5 10 INT1 P0 3 CLKOUT P0 1 VDD 12 17 7 8 TIO1 P0 6 TIO0 P0 5 28 27...

Страница 4: ...t It is therefore configured as an input to reduce current draw 26 22 16 15 14 21 P1 1 GPIO Port 1 bit 1 If this pin is used as a general purpose output it draws current It is therefore configured as...

Страница 5: ...nfigured individually Optional rising edge interrupt INT0 20 16 10 6 6 13 P0 3 INT1 GPIO port 0 bit 3 Configured individually Optional rising edge interrupt INT1 19 15 9 5 5 12 P0 4 INT2 GPIO port 0 b...

Страница 6: ...nable Int Act Low Reserved High Sink Open Drain Pull Up Enable Output Enable bb bbbb 00000000 11 13 P14CR P16CR SPI Use Int Enable Int Act Low Reserved High Sink Open Drain Pull Up Enable Output Enabl...

Страница 7: ...Int Enable bbb bbb 00000000 E1 INT_MSK1 TCAP0 Int Enable Prog Interval Timer Int Enable 1 ms Timer Int Enable Reserved bbb 00000000 E0 INT_MSK0 GPIO Port 1 Int Enable Sleep Timer Int Enable INT1 Int...

Страница 8: ...he user cannot manipulate the Supervisory State status bit 3 The flags are affected by arithmetic logic and shift opera tions The manner in which each flag is changed is dependent upon the instruction...

Страница 9: ...7 0 X 7 0 8 bit data value holds an index for any instruction that uses an indexed addressing mode Table 9 4 CPU Stack Pointer Register CPU_SP Bit 7 6 5 4 3 2 1 0 Field Stack Pointer 7 0 Read Write D...

Страница 10: ...is addressing mode is placed within either the RAM memory space or the register space Operand 1 is an address that points to the location of the result The source for the instruction is either the A r...

Страница 11: ...8 Destination Direct Source Direct The result of an instruction using this addressing mode is placed within the RAM memory Operand 1 is the address of the result Operand 2 is an address that points t...

Страница 12: ...by the Indirect address is moved into the Accumulator The indirect address is then incremented Table 9 16 Destination Indirect Post Increment Opcode Operand 1 Instruction Destination Address Address M...

Страница 13: ...expr 7A 7 2 DEC expr C Z 21 4 2 AND A expr Z 4E 5 1 SWAP A SP Z 7B 8 2 DEC X expr C Z 22 6 2 AND A expr Z 4F 4 1 MOV X SP 7C 13 3 LCALL 23 7 2 AND A X expr Z 50 4 2 MOV A expr Z 7D 7 3 LJMP 24 7 2 AN...

Страница 14: ...Full 0x0014 GPIO Port 0 0x0018 GPIO Port 1 0x001C INT1 0x0020 Reserved 0x0024 Reserved 0x0028 Reserved 0x002C Reserved 0x0030 Reserved 0x0034 1 ms Interval timer 0x0038 Programmable Interval Timer 0x...

Страница 15: ...rows are not affected by the device erase function 11 3 2 In System Programming enCoRe II LV devices enable in system programming by using the P1 0 and P1 1 pins as the serial programming mode interf...

Страница 16: ...er the SROM is entered with an M8C accumulator value of 00h the SRAM parameter block is not used as an input to the function This happens by design after a hardware reset because the M8C s accumulator...

Страница 17: ...ROMX instruction The ability to read using the SROM ReadBlock function is indicated by SR The protection level is stored in two bits according to Table 11 7 These bits are bit packed into 64 bytes of...

Страница 18: ...RAM while the Revision and Family IDs are returned in the CPU_A and CPU_X registers The Silicon ID is a value placed in the table by programming the Flash and is controlled by Cypress Semicon ductor P...

Страница 19: ...2 blk 1 F9h supervisory stack ptr key SSC_BLOCKID blk 1 FAh block ID SSC_POINTER blk 1 FBh pointer to data buffer SSC_CLOCK blk 1 FCh Clock SSC_MODE blk 1 FDh ClockW ClockE multiplier SSC_DELAY blk 1...

Страница 20: ...e parameter KEY2 holds the upper eight bits of the checksum The checksum algorithm executes the following sequence of three instructions over the number of blocks times 64 to be checksummed romx add K...

Страница 21: ...LV is initialized with 3 30V trim values at power on then firmware is responsible for transferring the correct set of trim values to the trim registers to match the application s actual Vdd The 32 kH...

Страница 22: ...ction circuitry allows the selection of independent clocks for the CPU Interval Timers and Capture Timers On the CY7C601xx the external oscillator is sourced by the crystal oscillator When the crystal...

Страница 23: ...P0 0 CLKIN P0 1 CLKOUT CY7C601xx only Table 12 2 CPU Clock Configuration CPUCLKCR 0x30 R W Bit 7 6 5 4 3 2 1 0 Field Reserved CPUCLK Select Read Write R W Default 0 0 0 0 0 0 0 0 Bit 7 1 Reserved Bit...

Страница 24: ...e 1 The Sleep Duty Cycle value is overridden The LVD and POR detection circuit is always enabled Note The periodic Sleep Duty Cycle enabling is independent with the sleep interval shown in the Sleep 1...

Страница 25: ...Table 12 4 Clock IO Configuration CLKIOCR 0x32 R W Bit 7 6 5 4 3 2 1 0 Field Reserved XOSC Select XOSC Enable EFTB Disabled CLKOUT Select Read Write R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7...

Страница 26: ...Hz low power oscillator A programmable prescaler of 2 4 6 or 8 then divides the selected source Figure 12 3 Timer Capture Block Diagram 12 bit reload value 12 bit down counter 12 bit reload control Cl...

Страница 27: ...t of the CLKIOCR Register is cleared Table 12 4 1 0 Internal 32 kHz Oscillator 1 1 TCAPCLK Disabled Note The 1024 s interval timer is based on the assumption that TCAPCLK is running at 4 MHz Changes i...

Страница 28: ...gain input A lower value of the gain setting increases the gain of the offset input This value sets the size of each offset step for the internal oscillator Nominal gain change KHz offsetStep at each...

Страница 29: ...Hz Bias Trim 1 0 32 kHz Freq Trim 3 0 Read Write R W R W R W R W R W R W R W Default 0 D D D D D D This register is used to calibrate the 32 kHz low speed oscillator The reset value is undefined but d...

Страница 30: ...IES bit is a legacy bit which was used to provide the ability to read the GIE bit of the CPU_F register However the CPU_F register is now readable When this bit is set it indicates that the GIE bit in...

Страница 31: ...r reduced states and the latency for the LVD is increased The actual latency is traded against power consumption by changing Sleep Duty Cycle field of the ECO_TR Register The internal 32 kHz low speed...

Страница 32: ...l oscil lator to reduce power to levels specified 14 1 1 Low Power in Sleep Mode To achieve the lowest possible power consumption during suspend or sleep the following conditions are observed in addit...

Страница 33: ...clock 2 At the following positive edge of the 32 kHz clock the system wide PD signal is negated The Flash memory module internal oscillator EFTB and bandgap circuit are all powered up to a normal oper...

Страница 34: ...PPOR detector generates a reset 0 0 2 7V Range trip near 2 6V 0 1 3V Range trip near 2 9V 1 0 Reserved 1 1 PPOR does not generate a reset but values read from the Voltage Monitor Comparators Register...

Страница 35: ...e trip point set by PORLEV 1 0 0 No precision power on reset event 1 A precision power on reset event has occurred Note This register exists in the second bank of IO space This requires setting the XI...

Страница 36: ...NT2 To configure the P0 4 P0 2 pins refer to the P0 2 INT0 P0 4 INT2 Configuration Register Table 16 8 Bit 1 P0 1 CLKOUT Beside its use as the P0 1 GPIO this pin is also used for the alternate functio...

Страница 37: ...active on the falling edge 16 2 3 TTL Thresh When set the input has TTL threshold When clear the input has standard CMOS threshold Note The GPIOs default to CMOS threshold User s firmware needs to con...

Страница 38: ...LK P1 5 SMOSI and P1 6 SMISO pins are used for their dedicated functions or for GPIO To enable the pin for GPIO clear the corresponding SPI Use bit The SPI function controls the output enable for its...

Страница 39: ...d Open Drain Pull up Enable Output Enable Read Write R W R W R W R W R W Default 0 0 0 0 0 0 0 0 These registers control the operation of pins P0 2 P0 4 respectively These pins are shared between the...

Страница 40: ...clock TIO1 P0 6 when enabled outputs a positive pulse from the programmable interval timer This is the same signal that is used internally to generate the programmable timer interval interrupt This s...

Страница 41: ...Default 0 0 0 0 0 0 0 0 This register controls the operation of the P1 2 Bit 7 CLK Output 0 The internally selected clock is not sent out onto P1 2 pin 1 This CLK Output is used to observe connected e...

Страница 42: ...onfigured for SPI SPI Use 1 and Comm Modes 1 0 SPI Master or SPI Slave mode the input and output direction of pins P1 5 and P1 6 is set automatically by the SPI logic However pin P1 4 s input and outp...

Страница 43: ...CY7C601xx this register controls the operation of pins P3 0 P3 7 The 50 mA sink drive capability is only available on pin P3 7 and only on CY7C601xx In CY7C602xx only 8 mA sink drive capability is av...

Страница 44: ...ram SPI State Machine SS_N Data 8 bit Load Empty Data 8 bit Load Full Sclk Output Enable Slave Select Output Enable Master IN Slave Out OE Master Out Slave In OE Shift Buffer Input Shift Buffer Output...

Страница 45: ...SMISO Among other things this is useful to implement single wire communi cations similar to SPI Bit 6 LSB First 0 The SPI transmits and receives the MSB Most Significant Bit first 1 The SPI transmits...

Страница 46: ...X X D AT A M S B B it 2 B it 3 B it 4 B it 5 B it 6 B it 7 LS B SCLK SSEL X X DAT A MSB Bit 2 B it 3 B it 4 Bit 5 Bit 6 Bit 7 LS B SCLK SSEL DATA X X MSB Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 LSB SCLK...

Страница 47: ...free running counter overflow occurs every 16 384 ms with a 4 MHz source This extends the length of the timer Figure 18 1 16 Bit Free Running Counter Block Diagram Table 17 4 SPI SCLK Frequency SCLK...

Страница 48: ...Bit 7 First Edge Hold The First Edge Hold function applies to all four capture timers 0 The time of the most recent edge is held in the Capture Timer Data Register If multiple edges have occurred sinc...

Страница 49: ...bits that are stored here are selected by the Prescale 2 0 bits in the Timer Configuration register When Capture 0 is in 16 bit mode this register holds the lower order eight bits of the 16 bit timer...

Страница 50: ...ains the status bits for the four timer captures for the four timer block capture interrupt sources Writing any of these bits with 1 clears that interrupt Bit 7 4 Reserved Bit 3 Cap1 Fall Active 0 No...

Страница 51: ...grammable Interval Reload Low PIRL 0x28 R W Bit 7 6 5 4 3 2 1 0 Field Prog Interval 7 0 Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 0 Prog Interval 7 0 This register holds...

Страница 52: ...CY7C601xx CY7C602xx Document 38 16016 Rev E Page 52 of 68 Figure 18 3 Timer Functional Sequence Diagram Feedback Feedback...

Страница 53: ...T reload ready Clk Timer 12b Prog Timer 12b reload interrupt Capture timer clk 16b free running counter load 16b free running counter 00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AB 00AC 00AD 0...

Страница 54: ...ts interrupt mask bit in the INT_MSKx register does not clear a posted interrupt nor does it prevent an interrupt from being posted It simply prevents a posted interrupt from becoming pending Nested i...

Страница 55: ...Flag registers CPU_PC and CPU_F The restored Flag register re enables interrupts since GIE 1 again 7 Execution resumes at the next instruction after the one that occurred before the interrupt However...

Страница 56: ...at are sometimes necessary to create a hardware only interrupt Table 19 3 Interrupt Clear 1 INT_CLR1 0xDB R W Bit 7 6 5 4 3 2 1 0 Field TCAP0 Prog Interval Timer 1 ms Program mable Interrupt Reserved...

Страница 57: ...upt Bit 3 Reserved Bit 2 INT2 Interrupt Enable 0 Mask INT2 interrupt 1 Unmask INT2 interrupt Bit 1 16 bit Counter Wrap Interrupt Enable 0 Mask 16 bit Counter Wrap interrupt 1 Unmask 16 bit Counter Wra...

Страница 58: ...it 3 SPI Receive Interrupt Enable 0 Mask SPI Receive interrupt 1 Unmask SPI Receive interrupt Bit 2 SPI Transmit Enable 0 Mask SPI Transmit interrupt 1 Unmask SPI Transmit interrupt Bit 1 INT0 Interru...

Страница 59: ...Current CPU 6 MHz Vdd 3 3V T 75C CPU 6 MHz Vdd 3 3V T 25C 3 15 2 45 9 mA mA ICC3 VCC Operating Supply Current CPU 3 MHz Vdd 2 7V T 25C 2 0 mA ISB1 Standby Current Internal and external oscillators Ba...

Страница 60: ...I Timing TSMCK SPI Master Clock Rate FCPUCLK 6 2 MHz TSSCK SPI Slave Clock Rate 2 2 MHz TSCKH SPI Clock High Time High for CPOL 0 Low for CPOL 1 125 ns TSCKL SPI Clock Low Time Low for CPOL 0 High for...

Страница 61: ...Figure 20 2 GPIO Timing Diagram Figure 20 3 SPI Master Timing CPHA 1 10 TR_GPIO TF_GPIO GPIO Pin Output Voltage 90 MSB TMSU LSB TMHD TSCKH TMDO SS SCK CPOL 0 SCK CPOL 1 MOSI MISO SS is under firmware...

Страница 62: ...ng CPHA 1 Figure 20 5 SPI Master Timing CPHA 0 MSB TSSU LSB TSHD TSCKH TSDO SS SCK CPOL 0 SCK CPOL 1 MOSI MISO TSCKL TSSS TSSH MSB LSB MSB TMSU LSB TMHD TSCKH TMDO1 SS SCK CPOL 0 SCK CPOL 1 MOSI MISO...

Страница 63: ...223 QXC 8K 256 24 QSOP 22 Package Handling Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving the factory A label on the p...

Страница 64: ...101 0 0118 0 299 0 0091 0 231 0 0125 0 317 0 015 0 381 0 050 1 270 0 013 0 330 0 019 0 482 0 026 0 660 0 032 0 812 0 004 0 101 PART S24 3 STANDARD PKG SZ24 3 LEAD FREE PKG MIN MAX NOTE 1 JEDEC STD RE...

Страница 65: ...Figure 23 4 28 Pin 5 3 mm Shrunk Small Outline Package O28 0 033 0 228 0 150 0 337 0 053 0 004 0 025 0 008 0 016 0 007 0 8 REF 0 344 0 157 0 244 BSC 0 012 0 010 0 069 0 034 0 010 SEATING PLANE MAX DIM...

Страница 66: ...CY7C601xx CY7C602xx Document 38 16016 Rev E Page 66 of 68 Figure 23 5 40 Pin 600 Mil Molded DIP P17 Figure 23 6 48 Pin Shrunk Small Outline Package O48 51 85019 A 51 85061 C Feedback Feedback...

Страница 67: ...n on sending receiving data when using 32 KHz oscillator B 505222 TYJ See ECN Minor text changes GPIO capacitance and timing diagram included Method to clear Capture Interrupt Status bit discussed Sle...

Страница 68: ...firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation...

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