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CYS25G0101DX-ATC Evaluation Board User’s Guide

14

5.3  Analog Line Loopback

In the Analog Line Loopback mode, serial data (from IN±) will loop through directly from serial input buffer to the serial output buffer
(OUT±). 

Figure 6

 shows the data path (bold line) of the Analog Line Loopback mode. To select the Analog Line Loopback mode:

1. SW1-4 (LOOPA) must be in ON position and SW1-3 (LINELOOP) must be in OFF position. 

2. All other dip switches must be in their default positions as stated in 

Table 4

3. TEST0, jumper J6 must be opened

4. Apply the Testing Hookup illustrated in 

Figure 8

 to 

Figure 10

Figure 6. Analog Line Loopback Mode Data Path

TXD
15:0

TX PLL

x16

/16

RXD

15:0

SHIFTER

RX CDR

PLL

Input

Register

Output

Register

FIFO

(5byte)

SHIFTER

/16

RXCLKOUT

REFCLK

TXCLK

TXCLKIN

DIAGLOOP
(SW1-2) = OFF

LINELOOP
SW1-3 = OFF

LOOPA
SW1-4 = ON

IN

±

OUT

±

[+] Feedback 

Содержание CYS25G0101DX-ATC

Страница 1: ...Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408 943 2600 March 19 2002 CYS25G0101DX ATC Evaluation Board User s Guide Feedback...

Страница 2: ...The Block Diagram of the CYS25G0101DX 5 Figure 2 The CYS25G0101DX Evaluation Board 6 Figure 3 The Jumper Orientations of the CYS25G0101DX 11 Figure 4 Diagnostic Loopback Mode Data Path 12 Figure 5 Li...

Страница 3: ...st of Tables Table 1 Functional Description of the Connectors 6 Table 2 Pin Assignment of J1 Header and Description of J10 Header 7 Table 3 Pin Assignment of J2 Header and Description of J9 Header 8 T...

Страница 4: ...he REFCLK of the CYS25G0101DX is connected to the onboard 155 52 MHz oscillator The on board REFCLK can be replaced by connecting the external reference clock source to J17 and J18 To use the external...

Страница 5: ...15 0 155 52MHz REFCLK 155 52MHz RXCLKOUT SHIFTER RX CDR PLL TXCLKO Input Register Output Register FIFO 5byte SHIFTER 155 52MHz TXCLKI 16 DIAGLOOP LINELOOP LOOPA IN OUT Lock to Data Clock Control Logi...

Страница 6: ...rdetails Figure 3showstheorienta tionofthisheader J2 TxDBUS 16 bitTxDDataBusinterfaceheader seeTable 3fordetails Figure 3showstheorienta tionofthisheader J3 TxCLKO_H HeaderforCYS25G0101DX sTXCLKO pin7...

Страница 7: ...MAconnectorforCYS25G0101DX sOUT pin103 Thisconnectorisalsofortheoption alopticalmoduleinterface SMA17 REFCLKP OptionalSMAconnectorforCYS25G0101DX sREFCLK pin87 Thisconnectorisforus ingtheexternalrefer...

Страница 8: ...X CLK 25 RXD3 HSTLoutput ParallelreceivedataoutputRXD3 TheoutputschangefollowingRX CLK 27 RXD2 HSTLoutput ParallelreceivedataoutputRXD2 TheoutputschangefollowingRX CLK 29 RXD1 HSTLoutput Parallelrecei...

Страница 9: ...putdataissampledbyTX CLKI 30 TXD1 HSTLinput ParalleltransmitdatainputTXD1 TheinputdataissampledbyTX CLKI 32 TXD0 HSTLinput ParalleltransmitdatainputTXD0 TheinputdataissampledbyTX CLKI J9 TXCLKI HSTLin...

Страница 10: ...maximumseparation Table 5 Functional Description of J4 Connector Pin Name Description 1A 1B 3A 3B VCC_OPTIC Powersupplyforopticalmodule 2A 2B 4A 4B GND Powerground 5A NC NoConnection 5B SD SDsignalfro...

Страница 11: ...G0101DX ATC Evaluation Board User s Guide 11 Figure 3 The Jumper Orientations of the CYS25G0101DX J7 J8 LFI GND GND FIFO_ERR RXCLK GND J1 Pin 1 Pin 1 GND GND TXCLKO TXCLKI J2 1 2 3 J5 5B 1B 1A 5A Feed...

Страница 12: ...e paralleldatawillloopthroughtheinputbuffer serializer CDRblock deserializerandtheoutputbuff er Figure 4showsthedatapath boldline oftheDiagnosticLoopbackmode ToselecttheDiagnosticLoopbackmode 1 SW1 2...

Страница 13: ...electtheLineLoopbackmode 1 SW1 3 LINELOOP mustbeinONposition 2 AllotherdipswitchsettingsmustbeintheirdefaultpositionsasstatedinTable 4 3 TEST0 jumperJ6mustbeopened 4 ApplytheTestingHookupillustratedin...

Страница 14: ...ogLineLoopbackmode 1 SW1 4 LOOPA mustbeinONpositionandSW1 3 LINELOOP mustbeinOFFposition 2 AllotherdipswitchesmustbeintheirdefaultpositionsasstatedinTable 4 3 TEST0 jumperJ6mustbeopened 4 ApplytheTest...

Страница 15: ...X CDR PLL and TX PLL 1 TEST0 jumperJ6mustbeshorted 2 Alldipswitchesmustbeintheirdefaultpositions seeTable 4 3 DisconnectCLKVCC P2 removethe155 52 MHzoscillator placeC400onC402andC401onC403positions se...

Страница 16: ...ionBoard 2 PatternGenerator TektronixD3186PatternGenerator 3 ErrorDetector TektronixD3286ErrorDetector 4 PowerSupply HPE3631ADCPowerSupply Allequipmentinthelistisforreferenceonly Figure 8 Equipment Se...

Страница 17: ...3186PatternGenerator 3 Oscilloscope AgilentInfiniiumDCA86100Awith83484ADual Channel50GHzModule 4 PowerSupply HPE3631ADCPowerSupply Allequipmentinthelistisforreferenceonly Figure 9 Equipment Set up For...

Страница 18: ...t HP OmniBER718CommunicationPerformanceAnalyzer 3 OpticalConverters Agilent HP 83446AReceiverand83430ATransmitter 4 PowerSupply HPE3631ADCPowerSupply Allequipmentinthelistisforreferenceonly Figure 10...

Страница 19: ...tor HP8133APulseGenerator 5 PowerSupply HPE3631ADCPowerSupply Allequipmentinthelistisforreferenceonly Figure 11 Equipment Set up For Testing the TX PLL in Parallel Line Loopback Mode IN IN OUT OUT Tek...

Страница 20: ...is the Eye Diagram measurement from CYS25G0101DX Evaluation Board by using the test set up as in Figure 9 In this measurement theevaluationboardisconfiguredtoparallelloopbackmode Figure 7 andwithnoSO...

Страница 21: ...gure 13isthemeasurement resultoftheGR 253 Bellcore standardandFigure 14isthemeasurementresultoftheG958 ITU standard Inthismeasurement the CYS25G0101DXevaluationboardisconfiguredtoparallelloopbackmode...

Страница 22: ...igure 15isthemeasurement resultoftheGR 253 Bellcore standardandFigure 16isthemeasurementresultoftheG825 ITU standard Inthismeasurement the CYS25G0101DXevaluationboardisconfiguredtoparallelloopbackmode...

Страница 23: ...dinAppendix C forLVPECLTable 8toTable 11 andAppendix D forHSTLTable 12toTable 15 respectively Notes 1 The operation voltage VCC for the device at the power supply nodes 2 The operation current drawn b...

Страница 24: ...CYS25G0101DX ATC Evaluation Board User s Guide 24 Appendix A Schematic Diagrams of the CYS25G0101DX Evaluation Board Feedback...

Страница 25: ...0101DX Evaluation Board Schematic Diagram Parallel Input Block Parallel Output Block Power Supply Block Control Block Reference Clock Block Signals Block o Parallel Input Block Parallel Output Block P...

Страница 26: ...CYS25G0101DX ATC Evaluation Board User s Guide 26 Figure 18 Parallel Output Block Schematic Diagram Feedback...

Страница 27: ...CYS25G0101DX ATC Evaluation Board User s Guide 27 Figure 19 Parallel Input Block Schematic Diagram Feedback...

Страница 28: ...CYS25G0101DX ATC Evaluation Board User s Guide 28 Figure 20 Signals Block Schematic Diagram Feedback...

Страница 29: ...CYS25G0101DX ATC Evaluation Board User s Guide 29 Figure 21 Power Supply Block Schematic Diagram Feedback...

Страница 30: ...CYS25G0101DX ATC Evaluation Board User s Guide 30 Figure 22 Control Block Schematic Diagram Feedback...

Страница 31: ...CYS25G0101DX ATC Evaluation Board User s Guide 31 Figure 23 Reference Clock Block Schematic Diagram Feedback...

Страница 32: ...CYS25G0101DX ATC Evaluation Board User s Guide 32 Appendix B PCB Layout Diagrams of the CYS25G0101DX Evaluation Board Feedback...

Страница 33: ...CYS25G0101DX ATC Evaluation Board User s Guide 33 Figure 24 CYS25G0101DX Evaluation Board PCB Mechanical Drawing Feedback...

Страница 34: ...CYS25G0101DX ATC Evaluation Board User s Guide 34 Figure 25 CYS25G0101DX Evaluation Board PCB Top Layer Silk Screen Feedback...

Страница 35: ...CYS25G0101DX ATC Evaluation Board User s Guide 35 Figure 26 CYS25G0101DX Evaluation Board PCB Top Layer Layout Feedback...

Страница 36: ...CYS25G0101DX ATC Evaluation Board User s Guide 36 Figure 27 CYS25G0101DX Evaluation Board PCB Top Layer Solder Mask Feedback...

Страница 37: ...CYS25G0101DX ATC Evaluation Board User s Guide 37 Figure 28 CYS25G0101DX Evaluation Board PCB Power Plane Layout Feedback...

Страница 38: ...CYS25G0101DX ATC Evaluation Board User s Guide 38 Figure 29 CYS25G0101DX Evaluation Board PCB Ground Plane Layout Feedback...

Страница 39: ...CYS25G0101DX ATC Evaluation Board User s Guide 39 Figure 30 CYS25G0101DX Evaluation Board PCB Bottom Silk Screen Feedback...

Страница 40: ...CYS25G0101DX ATC Evaluation Board User s Guide 40 Figure 31 CYS25G0101DX Evaluation Board PCB Bottom Layer Layout Feedback...

Страница 41: ...CYS25G0101DX ATC Evaluation Board User s Guide 41 Figure 32 CYS25G0101DX Evaluation Board PCB Bottom Solder Mask Feedback...

Страница 42: ...CYS25G0101DX ATC Evaluation Board User s Guide 42 Appendix C CYS25G0101DX Evaluation Board LVPECL BOM Bill of Material Feedback...

Страница 43: ...CYS25G0101DX ATC Evaluation Board User s Guide 43 Table 8 CYS25G0101DX Evaluation Board LVPECL BOM Page 1 of 4 Feedback...

Страница 44: ...CYS25G0101DX ATC Evaluation Board User s Guide 44 Table 9 CYS25G0101DX Evaluation Board LVPECL BOM Page 2 of 4 Feedback...

Страница 45: ...CYS25G0101DX ATC Evaluation Board User s Guide 45 Table 10 CYS25G0101DX Evaluation Board LVPECL BOM Page 3 of 4 Feedback...

Страница 46: ...CYS25G0101DX ATC Evaluation Board User s Guide 46 Table 11 CYS25G0101DX Evaluation Board LVPECL BOM Page 4 of 4 Feedback...

Страница 47: ...CYS25G0101DX ATC Evaluation Board User s Guide 47 Appendix D CYS25G0101DX Evaluation Board HSTL BOM Bill of Material Feedback...

Страница 48: ...CYS25G0101DX ATC Evaluation Board User s Guide 48 Table 12 CYS25G0101DX Evaluation Board HSTL BOM Page 1 of 4 Feedback...

Страница 49: ...CYS25G0101DX ATC Evaluation Board User s Guide 49 Table 13 CYS25G0101DX Evaluation Board HSTL BOM Page 2 of 4 Feedback...

Страница 50: ...CYS25G0101DX ATC Evaluation Board User s Guide 50 Table 14 CYS25G0101DX Evaluation Board HSTL BOM Page 3 of 4 Feedback...

Страница 51: ...y any license under patent or other rights Cypress Semiconductor does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be...

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