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PRELIMINARY

CY8CNP102B, CY8CNP102E

Document #: 001-43991 Rev. *D

Page 32 of 38

AC Programming Specifications

AC I

2

C Specifications

Table 39.  5V AC Programming Specifications (CY8CNP102E) 

Symbol

Description

Min

Typ

Max

Units

Notes

T

RSCLK

Rise Time of SCLK 

1

–

20

ns

T

FSCLK

Fall Time of SCLK 

1

–

20

ns

T

SSCLK

Data Set up Time to Falling Edge of SCLK

40

–

–

ns

T

HSCLK

Data Hold Time from Falling Edge of SCLK

40

–

–

ns

F

SCLK

Frequency of SCLK

0

–

8

MHz

T

ERASEB

Flash Erase Time (Block)

–

10

–

ms

T

WRITE

Flash Block Write Time

–

10

–

ms

T

DSCLK

Data Out Delay from Falling Edge of SCLK

–

–

45

ns

4.75V 

≤

 Vcc 

≤

 5.25V

Table 40.  5V AC Characteristics of the I

2

C SDA and SCL Pins (CY8CNP102E)

Symbol

Description

Standard Mode

Fast Mode

Units

Min

Max

Min

Max

F

SCLI2C

SCL Clock Frequency

0

100

0

400

kHz

T

HDSTAI2C

Hold Time (repeated) START Condition. After this 

period, the first clock pulse is generated.

4.0

–

0.6

–

μ

s

T

LOWI2C

LOW Period of the SCL Clock

4.7

–

1.3

–

μ

s

T

HIGHI2C

HIGH Period of the SCL Clock

4.0

–

0.6

–

μ

s

T

SUSTAI2C

Setup Time for a Repeated START Condition

4.7

–

0.6

–

μ

s

T

HDDATI2C

Data Hold Time

0

–

0

–

μ

s

T

SUDATI2C

Data Setup Time

250

–

100

[9]

–

ns

T

SUSTOI2C

Setup Time for STOP Condition

4.0

–

0.6

–

μ

s

T

BUFI2C

Bus Free Time Between a STOP and START Condition

4.7

–

1.3

–

μ

s

T

SPI2C

Pulse Width of spikes are suppressed by the input filter.

–

–

0

50

ns

[+] Feedback 

Содержание CY8CNP102B

Страница 1: ...aneous sampling Up to 820 SPS for each channel with 8 channel sampling and logging 16 Digital PSoC Blocks provide 8 to 32 bit timers counters and PWMs CRC and PRS Modules Up to 4 Full Duplex UARTs Multiple SPI Masters and Slaves Complex Peripherals by Combining Blocks Precision Programmable Clocking Internal 2 5 24 and 48 MHz Oscillator 24 and 48 MHz with optional 32 768 kHz Crystal Optional Exter...

Страница 2: ...PRELIMINARY CY8CNP102B CY8CNP102E Document 001 43991 Rev D Page 2 of 38 Logic Block Diagram Feedback ...

Страница 3: ...olumn Output 3 P0_1 IO I Analog Column Mux Input GPIO 4 P2_7 IO GPIO 5 P2_5 IO GPIO 6 P2_3 IO I Direct Switched Capacitor Block Input 7 P2_1 IO I Direct Switched Capacitor Block Input 8 Vcc Power Supply Voltage 9 DNU Reserved for test modes Do Not Use 10 DNU Reserved for test modes Do Not Use 11 DNU Reserved for test modes Do Not Use 12 DNU Reserved for test modes Do Not Use 13 DNU Reserved for te...

Страница 4: ...A2 Connect to Pin 50 EN_A2 to NV_A2 60 EN_O Connect to Pin 76 EN_O to NV_O 61 EN_C Connect to Pin 99 EN_C to NV_C 62 XRES Input Active high external reset Internal Pull down 63 VCAP Power External Capacitor connection for nvSRAM 64 Vcc Power Supply Voltage 65 P2_0 IO I Direct Switched Capacitor Block Input GPIO 66 P2_2 IO I Direct Switched Capacitor Block Input GPIO 67 P2_4 IO External Analog GND ...

Страница 5: ...ng Every pin also has the capability to generate a system interrupt on high level low level and change from last read nvSRAM Data Memory The nvSRAM memory block is byte addressable fast static RAM with a nonvolatile element in each memory cell The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides infinite read ...

Страница 6: ...electable as Incremental Delta Sigma and SAR Filters 2 4 6 or 8 pole band pass low pass and notch Amplifiers up to 4 with selectable gain to 48x Instrumentation amplifiers up to 2 with selectable gain to 93x Comparators up to 4 with 16 selectable thresholds DACs up to 4 with 6 to 9 bit resolution Multiplying DACs up to 4 with 6 to 9 bit resolution High current output drivers four with 40 mA drive ...

Страница 7: ...possible to change the selected components and regenerate the framework Design Browser The Design Browser enables users to select and import preconfigured designs into their project Users can easily browse a catalog of preconfigured designs to facilitate time to design Examples provided in the tools include a 300 baud modem LIN Bus master and slave fan controller and magnetic card reader Applicati...

Страница 8: ...are to cut your development time The user module Application Programming Interface API provides high level functions to control and respond to hardware events at run time The API also provides optional interrupt service routines that you can adapt as needed The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE These data sheets explain the in...

Страница 9: ...ists the PSoC NV device DC and AC electrical specifications Specifications are valid for 40o C TA 85o C and TJ 100o C except where noted Refer Table 14 on page 17 for electrical specifications on the Internal Main Oscillator IMO using SLIMO mode The following table lists the units of measure that are used in this data sheet Figure 4 Voltage versus CPU Frequency Figure 5 IMO Frequency Trim Options ...

Страница 10: ... 65o C degrade reliability TA Ambient Temperature with Power Applied 40 85 oC Vcc Supply Voltage on Vcc Relative to Vss 0 5 4 1 V VIO DC Input Voltage Vss 0 5 Vcc 0 5 V VIOZ DC Voltage Applied to Tri state Vss 0 5 Vcc 0 5 V IMIO Maximum Current into any Port Pin 25 50 mA IMAIO Maximum Current into any Port Pin Configured as Analog Driver 50 50 mA ESD Electro Static Discharge Voltage 2000 V Human B...

Страница 11: ...rent with POR LVD Sleep Timer WDT and internal slow oscillator active 5 mA nvSRAM in standby VREF Reference Voltage Bandgap 1 28 1 3 1 32 V Trimmed for appropriate Vcc Vcap Storage Capacitor between Vcap and Vss 61 68 82 uF 5V rated minimum Table 6 3 3V DC GPIO Specifications CY8CNP102B Symbol Description Min Typ Max Units Notes RPU Pull up Resistor 4 5 6 8 KΩ RPD Pull down Resistor 4 5 6 8 KΩ VOH...

Страница 12: ... μA CINOA Input Capacitance Port 0 Analog Pins 4 5 9 5 pF Pin dependent Temp 25 o C VCMOA Common Mode Voltage Range 0 Vcc V CMRROA Common Mode Rejection Ratio 60 dB GOLOA Open Loop Gain 80 dB VOHIGHOA High Output Voltage Swing internal signals Vcc 0 01 V VOLOWOA Low Output Voltage Swing internal signals 0 01 V ISOA Supply Current including associated AGND buffer Power Low Opamp Bias Low 150 200 μA...

Страница 13: ...ffset Voltage Drift 6 μV C VCMOB Common Mode Input Voltage Range 0 5 Vcc 1 0 V ROUTOB Output Resistance Power Low 10 Ω Power High 10 Ω VOHIGHOB High Output Voltage Swing Load 1KΩ to Vcc 2 Power Low 0 5 x Vcc 1 0 V Power High 0 5 x Vcc 1 0 V VOLOWOB Low Output Voltage Swing Load 1KΩ to Vcc 2 Power Low 0 5 x Vcc 1 0 V Power High 0 5 x Vcc 1 0 V ISOB Supply Current Including Bias Cell No Load Power L...

Страница 14: ...3V 1 28 1 30 1 32 V AGND Vcc 2 1 Vcc 2 0 02 Vcc 2 Vcc 2 0 02 V AGND 2 x BandGap 1 Not Allowed AGND P2 4 P2 4 Vcc 2 P2 4 0 009 P2 4 P2 4 0 009 V AGND BandGap 1 1 27 1 30 1 34 V AGND 1 6 x BandGap 1 2 03 2 08 2 13 V AGND Block to Block Variation AGND Vcc 2 1 0 034 0 000 0 034 mV RefHi Vcc 2 BandGap Not Allowed RefHi 3 x BandGap Not Allowed RefHi 2 x BandGap P2 6 P2 6 0 5V Not Allowed RefHi P2 4 Band...

Страница 15: ...PPOR Trip negative ramp VPPOR0 PORLEV 1 0 00b 2 82 V PPOR Hysteresis VPH0 PORLEV 1 0 00b 92 mV VPH1 PORLEV 1 0 01b 0 mV VPH2 PORLEV 1 0 10b 0 mV Vdd Value for LVD Trip VLVD0 VM 2 0 000b 2 86 2 92 2 98 2 V VLVD1 VM 2 0 001b 2 96 3 02 3 08 V VLVD2 VM 2 0 010b 3 07 3 13 3 20 V Vdd Value for SMP Trip VPUMP0 VM 2 0 000b 2 96 3 02 3 08 V VPUMP1 VM 2 0 001b 3 03 3 10 3 16 V VPUMP2 VM 2 0 010b 3 18 3 25 3...

Страница 16: ...ify Vss 0 75 V VOHV Output High Voltage During Programming or Verify Vcc 1 0 Vcc V FlashENPB Flash Endurance per block 50 000 Erase write cycles per block FlashENT Flash Endurance total 3 1 800 000 Erase write cycles FlashDR Flash Data Retention 10 Years Note 3 A maximum of 36 x 50 000 block endurance cycles is allowed This may be balanced between operations 36x1 blocks of 50 000 maximum cycles ea...

Страница 17: ...tor 32 768 kHz Accuracy is capacitor and crystal dependent 50 duty cycle FPLL PLL Frequency 23 986 MHz A multiple x732 of crystal frequency Jitter24M2 24 MHz Period Jitter PLL 600 ps TPLLSLEW PLL Lock Time 0 5 10 ms TPLLSLEWLOW PLL Lock Time for Low Gain Setting 0 5 50 ms TOS External Crystal Oscillator Startup to 1 250 500 ms TOSACC External Crystal Oscillator Startup to 100 ppm 300 600 ms The cr...

Страница 18: ...meter Description nvSRAM Unit Min Max tHRECALL Power Up RECALL Duration 20 ms tSTORE STORE Cycle Duration 12 5 ms VSWITCH Low Voltage Trigger Level 2 65 V tVccRISE VCC Rise Time 150 μs Table 16 3 3V AC GPIO Specifications CY8CNP102B Symbol Description Min Typ Max Units Notes FGPIO GPIO Operating Frequency 0 12 3 MHz Normal Strong Mode TRiseS Rise Time Slow Strong Mode Cload 50 pF 10 27 ns Vcc 3V t...

Страница 19: ...Falling Slew Rate 20 to 80 of a 1V Step 10 pF load Unity Gain Power Low Opamp Bias Low 0 24 V μs Power Medium Opamp Bias High 1 8 V μs BWOA Gain Bandwidth Product Power Low Opamp Bias Low 0 67 MHz Power Medium Opamp Bias High 2 8 MHz ENOA Noise at 1 kHz Power Medium Opamp Bias High 100 nV rt Hz Note 8 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz 42 ns nomin...

Страница 20: ...m data rate at 3 08 MHz due to 8 x over clocking Vcc 3 0V 2 Stop Bits 49 2 MHz Maximum data rate at 6 15 MHz due to 8 x over clocking Table 18 3 3V AC Digital Block Specifications CY8CNP102B continued Function Description Min Typ Max Units Notes Table 19 3 3V AC Analog Output Buffer Specifications CY8CNP102B Symbol Description Min Typ Max Units TROB Rising Settling Time to 0 1 1V Step 100pF Load P...

Страница 21: ...e repeated START Condition After this period the first clock pulse is generated 4 0 0 6 μs TLOWI2C LOW Period of the SCL Clock 4 7 1 3 μs THIGHI2C HIGH Period of the SCL Clock 4 0 0 6 μs TSUSTAI2C Setup Time for a Repeated START Condition 4 7 0 6 μs THDDATI2C Data Hold Time 0 0 μs TSUDATI2C Data Setup Time 250 100 9 ns TSUSTOI2C Setup Time for STOP Condition 4 0 0 6 μs TBUFI2C Bus Free Time Betwee...

Страница 22: ... 65o C degrade reliability TA Ambient Temperature with Power Applied 40 85 o C Vcc Supply Voltage on Vcc Relative to Vss 0 5 6 0 V VIO DC Input Voltage Vss 0 5 Vcc 0 5 V VIOZ DC Voltage Applied to Tri state Vss 0 5 Vcc 0 5 V IMIO Maximum Current into any Port Pin 25 50 mA IMAIO Maximum Current into any Port Pin Configured as Analog Driver 50 50 mA ESD Electro Static Discharge Voltage 2000 V Human ...

Страница 23: ...rrent with POR LVD Sleep Timer WDT and internal slow oscillator active 5 mA nvSRAM in standby VREF Reference Voltage Bandgap 1 28 1 3 1 32 V Trimmed for appropriate Vcc Vcap Storage Capacitor between Vcap and Vss 61 68 82 uF 5V rated minimum Table 25 5V DC GPIO Specifications CY8CNP102E Symbol Description Min Typ Max Units Notes RPU Pull up Resistor 4 5 6 8 kΩ RPD Pull down Resistor 4 5 6 8 kΩ VOH...

Страница 24: ...pacitance Port 0 Analog Pins 4 5 9 5 pF Pin dependent Temp 25 oC VCMOA Common Mode Voltage Range All Cases except highest 0 0 Vcc V Power High Opamp Bias High 0 5 Vcc 0 5 V CMRROA Common Mode Rejection Ratio 60 dB GOLOA Open Loop Gain 80 dB VOHIGHOA High Output Voltage Swing internal signals Vcc 0 01 V VOLOWOA Low Output Voltage Swing internal signals 0 1 V ISOA Supply Current including associated...

Страница 25: ... V Power High 0 5 x Vcc 1 3 V ISOB Supply Current Including Bias Cell No Load Power Low 1 1 2 mA Power High 2 6 5 mA PSRROB Supply Voltage Rejection Ratio 40 64 dB Table 29 5V DC Analog Reference Specifications CY8CNP102E Symbol Description Min Typ Max Units VBG5 Bandgap Voltage Reference 5V 1 28 1 30 1 32 V AGND Vcc 2 1 Vcc 2 0 02 Vcc 2 Vcc 2 0 02 V AGND 2 x BandGap 1 2 52 2 60 2 72 V AGND P2 4 P...

Страница 26: ...OR0 PORLEV 1 0 00b 2 82 V VPPOR1 PORLEV 1 0 01b 4 39 V VPPOR2 PORLEV 1 0 10b 4 55 V PPOR Hysteresis VPH0 PORLEV 1 0 00b 92 mV VPH1 PORLEV 1 0 01b 0 mV VPH2 PORLEV 1 0 10b 0 mV Vdd Value for LVD Trip VLVD0 VM 2 0 000b 2 86 2 92 2 98 2 V VLVD1 VM 2 0 001b 2 96 3 02 3 08 V VLVD2 VM 2 0 010b 3 07 3 13 3 20 V VLVD3 VM 2 0 011b 3 92 4 00 4 08 V VLVD4 VM 2 0 100b 4 39 4 48 4 57 V VLVD5 VM 2 0 101b 4 55 4...

Страница 27: ... 2 2 V IILP Input Current when Applying Vilp to P1 0 or P1 1 During Programming or Verify 0 2 mA Driving internal pull down resistor IIHP Input Current when Applying Vihp to P1 0 or P1 1 During Programming or Verify 1 5 mA Driving internal pull down resistor VOLV Output Low Voltage During Programming or Verify Vss 0 75 V VOHV Output High Voltage During Programming or Verify Vcc 1 0 Vcc V FlashENPB...

Страница 28: ...l Block Specifications on page 30 F24M Digital PSoC Block Frequency 0 24 24 6 5 7 MHz F32K1 Internal Low Speed Oscillator Frequency 15 32 64 kHz F32K2 External Crystal Oscillator 32 768 kHz Accuracy is capacitor and crystal dependent 50 duty cycle FPLL PLL Frequency 23 986 MHz A multiple x732 of crystal frequency Jitter24M2 24 MHz Period Jitter PLL 600 ps TPLLSLEW PLL Lock Time 0 5 10 ms TPLLSLEWL...

Страница 29: ...ter Description nvSRAM Unit Min Max tHRECALL Power Up RECALL Duration 20 ms tSTORE STORE Cycle Duration 12 5 ms VSWITCH Low Voltage Trigger Level 4 4 V tVccRISE VCC Rise Time 150 μs Table 35 5V AC GPIO Specifications CY8CNP102E Symbol Description Min Typ Max Units Notes FGPIO GPIO Operating Frequency 0 12 3 MHz Normal Strong Mode TRiseF Rise Time Normal Strong Mode Cload 50 pF 3 18 ns Vcc 4 75V to...

Страница 30: ...A Falling Slew Rate 20 to 80 of a 1V Step 10 pF load Unity Gain Power Low Opamp Bias Low 0 01 V μs Power Medium Opamp Bias High 0 5 V μs Power High Opamp Bias High 4 0 V μs BWOA Gain Bandwidth Product Power Low Opamp Bias Low 0 75 MHz Power Medium Opamp Bias High 3 1 MHz Power High Opamp Bias High 5 4 MHz ENOA Noise at 1 kHz Power Medium Opamp Bias High 100 nV rt Hz Table 37 5V AC Digital Block Sp...

Страница 31: ...at 3 08 MHz due to 8 x over clocking 49 2 MHz Maximum data rate at 6 15 MHz due to 8 x over clocking Table 38 5V AC Analog Output Buffer Specifications CY8CNP102E Symbol Description Min Typ Max Units TROB Rising Settling Time to 0 1 1V Step 100 pF Load Power Low 4 μs Power High 4 μs TSOB Falling Settling Time to 0 1 1V Step 100 pF Load Power Low 3 4 μs Power High 3 4 μs SRROB Rising Slew Rate 20 t...

Страница 32: ... SCLK 45 ns 4 75V Vcc 5 25V Table 40 5V AC Characteristics of the I2C SDA and SCL Pins CY8CNP102E Symbol Description Standard Mode Fast Mode Units Min Max Min Max FSCLI2C SCL Clock Frequency 0 100 0 400 kHz THDSTAI2C Hold Time repeated START Condition After this period the first clock pulse is generated 4 0 0 6 μs TLOWI2C LOW Period of the SCL Clock 4 7 1 3 μs THIGHI2C HIGH Period of the SCL Clock...

Страница 33: ...k for Low Gain Setting Timing Diagram VCC VSWITCH tSTORE tSTORE tHRECALL tHRECALL AutoStore POWER UP RECALL Read Write Inhibited STORE occurs only if a SRAM write has happened No STORE occurs without atleast one SRAM write tVCCRISE 2 4 M H z F P L L P L L E n a b le T P L L S L E W P L L G a in 0 2 4 M H z F P L L P L L E n a b l e T P L L S L E W L O W P L L G a in 1 Feedback ...

Страница 34: ...ram Figure 13 32 kHz Period Jitter ECO Timing Diagram Figure 14 Definition of Timing for Fast Standard Mode on the I2 C Bus Switching Waveforms continued 3 2 k H z F 3 2 K 2 3 2 K S e l e c t T O S J it t e r 2 4 M 1 F 2 4 M J it t e r 3 2 k F 3 2 K 2 S Sr tSUSTOI2C tSUSTAI2C tHDSTAI2C tHIGHI2C tLOWI2C tSUDATI2C tHDDATI2C tf SDA SCL P S tBUFI2C tr tf tr tSPI2C tHDSTAI2C Feedback ...

Страница 35: ...02 2Mb 12 512Kb B 3 3V E 5V A 100TQFP X Pb free C Commercial I Industrial Temp Ordering Information Ordering Code Package Diagram Package Type Operating Range CY8CNP102B AXI 51 85048 100 pin TQFP Industrial CY8CNP102E AXI 51 85048 100 pin TQFP All the above mentioned parts are of Pb free type and contain preliminary information Please contact your local Cypress sales representative for availabilit...

Страница 36: ...s may require a larger area on the target PCB than the chip s footprint For a detailed description of the emulation tool dimensions refer to the document PSoC Emulator Pod Dimensions at http www cypress com design MR10161 Thermal Impedance Package Diagrams Figure 15 100 Pin TQFP 14 x 14 x 1 4 mm 51 85048 C Note 10 TJ TA POWER x θJA Table 41 Thermal Impedance Package 10 Typical θJA Typical θJC 100 ...

Страница 37: ...anged IDDP naming convention to IDDPV Table 14 Updated note references Table 17 Updated Timer Counter deadband and CRCPS PRS mode values Table 23 Changed Typ and max value of IDD from 28 mA and 34 mA to 39 mA and 45 mA resp Table 23 Changed Typ and max value of IDDP from 15 mA and 16 mA to 27 mA and 28 mA resp Table 23 Changed Min and Max value of VCAP from 56 uF and 100 uF to 61 uF and 82 uF resp...

Страница 38: ... works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited...

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