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CY7C68033/CY7C68034

Document #: 001-04247 Rev. *D

Page 18 of 33

Register Summary

NX2LP-Flex register bit definitions are described in the EZ-USB TRM in greater detail. Some registers that are listed here and in
the TRM do not apply to the NX2LP-Flex. They are kept here for consistency reasons only. Registers that do not apply to the
NX2LP-Flex should be left at their default power-up values.

Table 9. NX2LP-Flex Register Summary

Hex

Size Name

Description

Default

Access

GPIF Waveform Memories

E400 128 WAVEDATA

GPIF Waveform
Descriptor 0, 1, 2, 3 data

xxxxxxxx

E480 128 reserved

GENERAL CONFIGURATION

E50D

GPCR2

General Purpose Configu-
ration Register 2

reserved

FULL_SPEE
D_ONLY

reserved

00000000 R

E600 1

CPUCS

CPU Control & Status

PORTCSTB CLKSPD1

CLKSPD0

CLKINV

CLKOE

8051RES

00000010 rrbbbbbr

E601 1

IFCONFIG

Interface Configuration
(Ports, GPIF, slave FIFOs)

3048MHZ

IFCLKPOL

ASYNC

GSTATE

IFCFG1

IFCFG0

10000000 RW

E602 1

PINFLAGSAB

[7]

Slave FIFO FLAGA and
FLAGB Pin Configuration

FLAGB3

FLAGB2

FLAGB1

FLAGB0

FLAGA3

FLAGA2

FLAGA1

FLAGA0

00000000 RW

E603 1

PINFLAGSCD

[7]

Slave FIFO FLAGC and
FLAGD Pin Configuration

FLAGD3

FLAGD2

FLAGD1

FLAGD0

FLAGC3

FLAGC2

FLAGC1

FLAGC0

00000000 RW

E604 1

FIFORESET

[7]

Restore FIFOS to default
state

NAKALL

EP3

EP2

EP1

EP0

xxxxxxxx

E605 1

BREAKPT

Breakpoint Control

BREAK

BPPULSE

BPEN

00000000 rrrrbbbr

E606 1

BPADDRH

Breakpoint Address H

A15

A14

A13

A12

A11

A10

xxxxxxxx

E607 1

BPADDRL

Breakpoint Address L

xxxxxxxx

E608 1

UART230

230 Kbaud internally
generated ref. clock

230UART1

230UART0

00000000 rrrrrrbb

E609 1

FIFOPINPOLAR

[7]

Slave FIFO Interface pins
polarity

PKTEND

SLOE

SLRD

SLWR

00000000 rrbbbbbb

E60A 1

REVID

Chip Revision

rv7

rv6

rv5

rv4

rv3

rv2

rv1

rv0

RevA
00000001

E60B 1

REVCTL

[7]

Chip Revision Control

dyn_out

enh_pkt

00000000 rrrrrrbb

UDMA

E60C 1

GPIFHOLDAMOUNT MSTB Hold Time

(for UDMA)

HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb

reserved

ENDPOINT CONFIGURATION

E610 1

EP1OUTCFG

Endpoint 1-OUT
Configuration

VALID

TYPE1

TYPE0

10100000 brbbrrrr

E611 1

EP1INCFG

Endpoint 1-IN
Configuration

VALID

TYPE1

TYPE0

10100000 brbbrrrr

E612 1

EP2CFG

Endpoint 2 Configuration VALID

DIR

TYPE1

TYPE0

SIZE

BUF1

BUF0

10100010 bbbbbrbb

E613 1

EP4CFG

Endpoint 4 Configuration VALID

DIR

TYPE1

TYPE0

10100000 bbbbrrrr

E614 1

EP6CFG

Endpoint 6 Configuration VALID

DIR

TYPE1

TYPE0

SIZE

BUF1

BUF0

11100010 bbbbbrbb

E615 1

EP8CFG

Endpoint 8 Configuration VALID

DIR

TYPE1

TYPE0

11100000 bbbbrrrr

reserved

E618 1

EP2FIFOCFG

[7]

Endpoint 2/slave FIFO
configuration

INFM1

OEP1

AUTOOUT

AUTOIN

ZEROLENIN 0

WORDWIDE 00000101 rbbbbbrb

E619 1

EP4FIFOCFG

[7]

Endpoint 4/slave FIFO
configuration

INFM1

OEP1

AUTOOUT

AUTOIN

ZEROLENIN 0

WORDWIDE 00000101 rbbbbbrb

E61A 1

EP6FIFOCFG

[7]

Endpoint 6/slave FIFO
configuration

INFM1

OEP1

AUTOOUT

AUTOIN

ZEROLENIN 0

WORDWIDE 00000101 rbbbbbrb

E61B 1

EP8FIFOCFG

[7]

Endpoint 8/slave FIFO
configuration

INFM1

OEP1

AUTOOUT

AUTOIN

ZEROLENIN 0

WORDWIDE 00000101 rbbbbbrb

E61C 4

reserved

E620 1

EP2AUTOINLENH

Endpoint 2 AUTOIN

Packet Length H

PL10

PL9

PL8

00000010 rrrrrbbb

E621 1

EP2AUTOINLENL

[7]

Endpoint 2 AUTOIN
Packet Length L

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

00000000 RW

E622 1

EP4AUTOINLENH

[7]

Endpoint 4 AUTOIN
Packet Length H

PL9

PL8

00000010 rrrrrrbb

E623 1

EP4AUTOINLENL

[7]

Endpoint 4 AUTOIN
Packet Length L

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

00000000 RW

E624 1

EP6AUTOINLENH

[7]

Endpoint 6 AUTOIN
Packet Length H

PL10

PL9

PL8

00000010 rrrrrbbb

E625 1

EP6AUTOINLENL

[7]

Endpoint 6 AUTOIN
Packet Length L

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

00000000 RW

E626 1

EP8AUTOINLENH

[7]

Endpoint 8 AUTOIN
Packet Length H

PL9

PL8

00000010 rrrrrrbb

E627 1

EP8AUTOINLENL

[7]

Endpoint 8 AUTOIN
Packet Length L

PL7

PL6

PL5

PL4

PL3

PL2

PL1

PL0

00000000 RW

E628 1

ECCCFG

ECC Configuration

ECCM

00000000 rrrrrrrb

Note

7. Read and writes to these registers may require synchronization delay, see the Technical Reference Manual for “Synchronization Delay.”

[+] Feedback

Содержание CY7C68033

Страница 1: ...our clocks per instruction cycle Three counter timers Expanded interrupt system Two data pointers 3 3V operation with 5V tolerant inputs Vectored USB interrupts and GPIF FIFO interrupts Separate data buffers for the Set up and Data portions of a CONTROL transfer Integrated I2 C controller runs at 100 or 400 kHz Four integrated FIFOs Integrated glue logic and FIFOs lower system cost Automatic conve...

Страница 2: ...ompile options for the default firmware allow for quick configuration of some features to decrease design effort and increase time to market advantages Overview Cypress Semiconductor Corporation s Cypress s EZ USB NX2LP Flex CY7C68033 CY7C68034 is a firmware based programmable version of the EZ USB NX2LP CY7C68023 CY7C68024 which is a fixed function low power USB 2 0 NAND Flash controller By integ...

Страница 3: ...unters divide it down for use as the 8051 clock The default 8051 clock frequency is 12 MHz The clock frequency of the 8051 can be changed by the 8051 through the CPUCS register dynamically Figure 3 Crystal Configuration Special Function Registers Certain 8051 SFR addresses are populated to provide fast access to critical NX2LP Flex functions These SFR additions are shown in Table 1 Bold type indic...

Страница 4: ...o NAND Flash is detected or if no valid firmware is found the NX2LP Flex uses the default values from internal ROM space for manufacturing mode operation The two modes of operation are described in the section Normal Operation Mode on page 5 and Manufacturing Mode on page 5 Table 1 Special Function Registers x 8x 9x Ax Bx Cx Dx Ex Fx 0 IOA IOB IOC IOD SCON1 PSW ACC B 1 SP EXIF INT2CLR IOE SBUF1 2 ...

Страница 5: ...re tools to enable first time NAND programming It is only available when used in conjunction with the NX2LP Flex Manufacturing tools and is not enabled during normal operation Bus powered Applications The NX2LP Flex fully supports bus powered designs by enumerating with less than 100 mA as required by the USB 2 0 specification Interrupt System INT2 Interrupt Request and Enable Registers NX2LP Flex...

Страница 6: ...eset 6 0x514 HISPEED Entered high speed operation 7 0x518 EP0ACK NX2LP ACK d the CONTROL Handshake 8 0x51C Reserved 9 0x520 EP0 IN EP0 IN ready to be loaded with data 10 0x524 EP0 OUT EP0 OUT has USB data 11 0x528 EP1 IN EP1 IN ready to be loaded with data 12 0x52C EP1 OUT EP1 OUT has USB data 13 0x530 EP2 IN buffer available OUT buffer has data 14 0x534 EP4 IN buffer available OUT buffer has data...

Страница 7: ... time reset is asserted while power is being applied to the circuit A powered reset is defined to be when the NX2LP Flex has previously been powered on and operating and the RESET pin is asserted Cypress provides an application note which describes and recommends power on reset implementation and can be found on the Cypress web site For more information on reset imple mentation for the EZ USB fami...

Страница 8: ...lly ORed to allow the 8051 to access it as both program and data memory No USB control registers appear in this space Internal Code Memory This mode implements the internal block of RAM starting at 0x0500 as combined code and data memory as shown in Figure 6 below Only the internal and scratch pad RAM spaces have the following access USB download only supported by the Cypress Manufac turing Tool S...

Страница 9: ...n though a buffer is configured to be a 512 byte buffer in full speed only the first 64 bytes are used The unused endpoint buffer space is not available for other opera tions An example endpoint configuration would be EP2 1024 double buffered EP6 512 quad buffered column 8 in Figure 8 Figure 8 Endpoint Configuration Default Full Speed Alternate Settings 64 64 64 512 512 1024 1024 1024 1024 1024 10...

Страница 10: ...h endpoint can individually be selected for byte or word operation by an internal configuration bit and a Slave FIFO Output Enable signal SLOE enables data of the selected width External logic must ensure that the output enable signal is inactive when writing data to a slave FIFO The slave interface must operate asynchronously where the SLRD and SLWR signals act directly as strobes rather than a c...

Страница 11: ...wo bit error ECCM 0 Two 3 byte ECCs each calculated over a 256 byte block of data This configuration conforms to the SmartMedia Standard and is used by both the NAND boot logic and default NAND firmware image When any value is written to ECCRESET and data is then passed across the GPIF or Slave FIFO interface the ECC for the first 256 bytes of data will be calculated and stored in ECC1 The ECC for...

Страница 12: ... package and lists pin names for all modes of operation Pin names with an asterisk feature programmable polarity Figure 9 Port and Signal Mapping XTALIN XTALOUT RESET WAKEUP SCL SDATA DPLUS DMINUS RDY0 RDY1 CTL0 CTL1 CTL2 PA7 PA6 PA5 PA4 PA3 WU2 PA2 PA1 INT1 PA0 INT0 GPIO8 GPIO9 FD 15 FD 14 FD 13 FD 12 FD 11 FD 10 FD 9 FD 8 FD 7 FD 6 FD 5 FD 4 FD 3 FD 2 FD 1 FD 0 SLRD SLWR FLAGA FLAGB FLAGC FLAGD ...

Страница 13: ...42 41 40 39 38 37 36 35 34 33 32 31 30 29 RESET GND PA7 FLAGD SLCS PA6 PKTEND PA5 FIFOADR1 PA4 FIFOADR0 PA3 WU2 PA2 SLOE PA1 INT1 PA0 INT0 VCC CTL2 FLAGC CTL1 FLAGB CTL0 FLAGA RDY0 SLRD RDY1 SLWR AVCC XTALOUT XTALIN AGND AVCC DPLUS DMINUS AGND VCC GND GPIO8 RESERVED VCC WAKEUP PD0 FD8 PD1 FD9 PD2 FD10 PD3 FD11 PD4 FD12 PD5 FD13 PD6 FD14 PD7 FD15 GND GPIO9 VCC GND GND VCC GND PB7 FD7 PB6 FD6 PB5 FD...

Страница 14: ... to FD 7 0 or FD 15 0 R_B1 is a NAND Ready Busy input signal 2 RDY1 or SLWR R_B2 Input N A Multiplexed pin whose function is selected by IFCONFIG 1 0 RDY1 is a GPIF input signal SLWR is the input only write strobe with programmable polarity FIFOPINPOLAR 2 for the slave FIFOs connected to FD 7 0 or FD 15 0 R_B2 is a NAND Ready Busy input signal 29 CTL0 or FLAGA WE O Z H Multiplexed pin whose functi...

Страница 15: ...LOE LED1 I O Z I PA2 Multiplexed pin whose function is selected by IFCONFIG 1 0 PA2 is a bidirectional IO port pin SLOE is an input only output enable with programmable polarity FIFOPINPOLAR 4 for the slave FIFOs connected to FD 7 0 or FD 15 0 LED1 is the data activity indicator LED sink pin 36 PA3 or WU2 LED2 I O Z I PA3 Multiplexed pin whose function is selected by WAKEUP 7 and OEA 3 PA3 is a bi...

Страница 16: ... bus DD2 is a bidirectional NAND data bus signal 21 PB3 or FD 3 DD3 I O Z I PB3 Multiplexed pin whose function is selected by IFCONFIG 1 0 PB3 is a bidirectional I O port pin FD 3 is the bidirectional FIFO GPIF data bus DD3 is a bidirectional NAND data bus signal 22 PB4 or FD 4 DD4 I O Z I PB4 Multiplexed pin whose function is selected by IFCONFIG 1 0 PB4 is a bidirectional I O port pin FD 4 is th...

Страница 17: ...3 CE5 or GPIO5 I O Z I PD5 Multiplexed pin whose function is selected by the IFCONFIG 1 0 and EPxFIFOCFG 0 wordwide bits FD 13 is the bidirectional FIFO GPIF data bus CE5 is a NAND chip enable output signal GPIO5 is a general purpose I O signal 51 PD6 or FD 14 CE6 or GPIO6 I O Z I PD6 Multiplexed pin whose function is selected by the IFCONFIG 1 0 and EPxFIFOCFG 0 wordwide bits FD 14 is the bidirec...

Страница 18: ...DAMOUNT MSTB Hold Time for UDMA 0 0 0 0 0 0 HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb 3 reserved ENDPOINT CONFIGURATION E610 1 EP1OUTCFG Endpoint 1 OUT Configuration VALID 0 TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr E611 1 EP1INCFG Endpoint 1 IN Configuration VALID 0 TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr E612 1 EP2CFG Endpoint 2 Configuration VALID DIR TYPE1 TYPE0 SIZE 0 BUF1 BUF0 10100010 bbbbbrbb E613 1...

Страница 19: ...able Flag L IN PKTS 1 OUT PFC7 IN PKTS 0 OUT PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW E636 H S 1 EP8FIFOPFH 7 Endpoint 8 slave FIFO Programmable Flag H DECIS PKTSTAT 0 IN PKTS 1 OUT PFC10 IN PKTS 0 OUT PFC9 0 0 PFC8 00001000 bbrbbrrb E636 F S 1 EP8FIFOPFH 7 Endpoint 8 slave FIFO Programmable Flag H DECIS PKTSTAT 0 OUT PFC10 OUT PFC9 0 0 PFC8 00001000 bbrbbrrb E637 H S 1 EP8FIFOPFL 7 Endpoint...

Страница 20: ...6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW E67C 1 XAUTODAT2 Autoptr2 MOVX access when APTREN 1 D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW UDMA CRC E67D 1 UDMACRCH 7 UDMA CRC MSB CRC15 CRC14 CRC13 CRC12 CRC11 CRC10 CRC9 CRC8 01001010 RW E67E 1 UDMACRCL 7 UDMA CRC LSB CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0 10111010 RW E67F 1 UDMACRC QUALIFIER UDMA CRC Qualifier QENABLE 0 0 0 QSTATE QSIGNAL2 QSIGNAL1 QSIGNAL0 0000000...

Страница 21: ...nt L BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R E6B3 1 SUDPTRH Setup Data Pointer high address byte A15 A14 A13 A12 A11 A10 A9 A8 xxxxxxxx RW E6B4 1 SUDPTRL Setup Data Pointer low ad dress byte A7 A6 A5 A4 A3 A2 A1 0 xxxxxxx0 bbbbbbbr E6B5 1 SUDPTRCTL Setup Data Pointer Auto Mode 0 0 0 0 0 0 0 SDPAUTO 00000001 RW 2 reserved E6B8 8 SET UPDAT 8 bytes of setup data D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx R ...

Страница 22: ...rog flag 0 0 0 0 0 0 0 FIFO8FLAG 00000000 RW E6EC 1 EP8GPIFTRIG 7 Endpoint 8 GPIF Trigger x x x x x x x x xxxxxxxx W 3 reserved E6F0 1 XGPIFSGLDATH GPIF Data H 16 bit mode only D15 D14 D13 D12 D11 D10 D9 D8 xxxxxxxx RW E6F1 1 XGPIFSGLDATLX Read Write GPIF Data L trigger transaction D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW E6F2 1 XGPIFSGLDATL NOX Read GPIF Data L no transaction trigger D7 D6 D5 D4 D3 D2...

Страница 23: ...ddressable D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW A1 1 INT2CLR 9 Interrupt 2 clear x x x x x x x x xxxxxxxx W A2 1 INT4CLR 9 Interrupt 4 clear x x x x x x x x xxxxxxxx W A3 5 reserved A8 1 IE Interrupt Enable bit addressable EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 00000000 RW A9 1 reserved AA 1 EP2468STAT 9 Endpoint 2 4 6 8 status flags EP8F EP8E EP6F EP6E EP4F EP4E EP2F EP2E 01011010 R AB 1 EP24FIFOFLGS 9 En...

Страница 24: ... 1 reserved CA 1 RCAP2L Capture for Timer 2 au to reload up counter D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW CB 1 RCAP2H Capture for Timer 2 au to reload up counter D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW CC 1 TL2 Timer 2 reload L D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW CD 1 TH2 Timer 2 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW CE 2 reserved D0 1 PSW Program Status Word bit addressable CY AC F0 RS1 RS...

Страница 25: ... Voltage 0 5 0 8 V II Input Leakage Current 0 VIN VCC 10 μA VOH Output Voltage HIGH IOUT 4 mA 2 4 V VOL Output LOW Voltage IOUT 4 mA 0 4 V IOH Output Current HIGH 4 mA IOL Output Current LOW 4 mA CIN Input Pin Capacitance Except D D 10 pF D D 15 pF ISUSP Suspend Current Connected 300 380 12 μA CY7C68034 Disconnected 100 150 12 μA Suspend Current Connected 0 5 1 2 12 mA CY7C68033 Disconnected 0 3 1...

Страница 26: ...d 10 5 ns tOEoff SLOE Turn off to FIFO Data Hold 10 5 ns SLRD FLAGS tRDpwl tRDpwh SLOE tXFLG tXFD DATA tOEon tOEoff N 1 N DATA tSFD tFDH FLAGS tXFD SLWR SLCS tWRpwh tWRpwl Notes 13 Dashed lines denote signals with programmable polarity 14 GPIF asynchronous RDYx signals have a minimum setup time of 50 ns when using internal 48 MHz IFCLK 15 Slave FIFO asynchronous parameter values use internal IFCLK...

Страница 27: ...n Min Max Unit tPEpwl PKTEND Pulse Width LOW 50 ns tPWpwh PKTEND Pulse Width HIGH 50 ns tXFLG PKTEND to FLAGS Output Propagation Delay 115 ns Table 14 Slave FIFO Output Enable Parameters Parameter Description Min Max Unit tOEon SLOE Assert to FIFO DATA Output 10 5 ns tOEoff SLOE Deassert to FIFO DATA Hold 10 5 ns Table 15 Slave FIFO Address to Flags Data Parameters Parameter Description Min Max Un...

Страница 28: ...ve FIFO Asynchronous Address Parameters 15 Parameter Description Min Max Unit tSFA FIFOADR 1 0 to SLRD SLWR PKTEND Setup Time 10 ns tFAH RD WR PKTEND to FIFOADR 1 0 Hold Time 10 ns SLRD FLAGS SLOE DATA tRDpwh tRDpwl tOEon tXFD tXFLG N Data X tXFD N 1 tXFD tOEoff N 3 N 2 tOEoff tXFLG tSFA tFAH FIFOADR SLCS Driven tXFD tOEon tRDpwh tRDpwl tRDpwh tRDpwl tRDpwh tRDpwl tFAH tSFA N t 0 T 0 T 1 T 7 T 2 T...

Страница 29: ...timing relationship of the SLAVE FIFO write in an asynchronous mode The diagram shows a single write followed by a burst write of 3 bytes and committing the 4 byte short packet using PKTEND At t 0 the FIFO address is applied insuring that it meets the setup time of tSFA If SLCS is used it must also be asserted SLCS may be tied low in some applications At t 1 SLWR is asserted SLWR must meet the min...

Страница 30: ...0 0 020 0 05 0 002 MAX 2 4X C 0 24 0 009 0 20 0 008 REF 0 80 0 031 MAX PIN1 ID 0 12 6 45 0 254 8 10 0 319 7 80 0 307 6 55 0 258 0 45 0 018 0 20 0 008 R 8 10 0 319 7 90 0 311 7 80 0 307 7 70 0 303 DIA 0 28 0 011 0 30 0 012 6 55 0 258 6 45 0 254 0 60 0 024 N 1 2 TOP VIEW BOTTOM VIEW SIDE VIEW E PAD PAD SIZE VARY BY DEVICE TYPE OPTION FOR CML BOTTOM VIEW NOTE DIMENSIONS ARE SAME WITH STD DWG ON UPPER...

Страница 31: ...ground plane by a 5 x 5 array of vias A via is a plated through hole in the PCB with a finished diameter of 13 mil The QFN s metal die paddle must be soldered to the PCB s thermal pad Solder mask is placed on the board top side over each via to resist solder flow into the via The mask on the top side also minimizes outgassing during the solder reflow process For further information on this package...

Страница 32: ...re a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Figure 22 Plot of the Solder Mask White Area Figure 23 X ray Image of the Assembly Purchase of I2C components from C...

Страница 33: ...XUT Minor Change Upload data sheet to external website Publicly announcing the parts No physical changes to document were made B 400518 See ECN GIR Took Preliminary off the top of all pages Corrected the first bulleted item Corrected Figure 3 2 caption Added new logo C 433952 See ECN RGL Added I2 C functionality D 498295 See ECN KKU Updated Data sheet format Changed In Output reference from I O to...

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