Cypress Semiconductor CY7C1480V25 Скачать руководство пользователя страница 21

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CY7C1480V25
CY7C1482V25
CY7C1486V25

Document #: 38-05282 Rev. *H

Page 21 of 32

Notes

15. Timing reference level is 1.25V when V

DDQ

= 2.5V and is 0.9V when V

DDQ

= 1.8V.

16. Test conditions shown in (a) of

“AC Test Loads and Waveforms” on page 20

unless otherwise noted.

17. This part has a voltage regulator internally; t

POWER

is the time that the power needs to be supplied above V

(minimum) initially before a read or write operation

can be initiated.

18. t

CHZ

, t

CLZ

, t

OELZ

, and t

OEHZ

are specified with AC test conditions shown in part (b) of AC Test Loads and Waveforms. Transition is measured ±200 mV from

steady-state voltage.

19. At any possible voltage and temperature, t

OEHZ

is less than t

OELZ

and t

CHZ

is less than t

CLZ

to eliminate bus contention between SRAMs when sharing the same

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z before Low-Z under the same system conditions.

20. This parameter is sampled and not 100% tested.

Switching Characteristics

Over the Operating Range

[15, 16]

Parameter

Description

250 MHz

200 MHz

167 MHz

Unit

Min.

Max.

Min.

Max.

Min.

Max.

POWER

(Typical) to the first access

[17]

Clock

CYC

Clock Cycle Time

4.0

5.0

6.0

Clock HIGH

2.0

2.4

Clock LOW

2.0

2.4

Output Times

Data Output Valid After CLK Rise

3.0

3.4

DOH

Data Output Hold After CLK Rise

1.3

1.5

CLZ

Clock to Low-Z

[18, 19, 20]

1.3

1.5

CHZ

Clock to High-Z

[18, 19, 20]

3.0

3.4

OEV

OE LOW to Output Valid

3.0

3.4

OELZ

OE LOW to Output Low-Z

[18, 19, 20]

OEHZ

OE HIGH to Output High-Z

[18, 19, 20]

3.0

3.4

Setup Times

Address Setup Before CLK Rise

1.4

1.5

ADS

ADSC, ADSP Setup Before CLK Rise

1.4

1.5

ADVS

ADV Setup Before CLK Rise

1.4

1.5

WES

GW, BWE, BW

Setup Before CLK Rise

1.4

1.5

Data Input Setup Before CLK Rise

1.4

1.5

CES

Chip Enable Setup Before CLK Rise

1.4

1.5

Hold Times

Address Hold After CLK Rise

0.4

0.5

ADH

ADSP, ADSC Hold After CLK Rise

0.4

0.5

ADVH

ADV Hold After CLK Rise

0.4

0.5

WEH

GW, BWE, BW

Hold After CLK Rise

0.4

0.5

Data Input Hold After CLK Rise

0.4

0.5

CEH

Chip Enable Hold After CLK Rise

0.4

0.5

[+] Feedback

Содержание CY7C1480V25

Страница 1: ...ntrolled by a positive edge triggered Clock Input CLK The synchronous inputs include all addresses all data inputs address pipelining Chip Enable CE1 depth expansion Chip Enables CE2 and CE3 Burst Control inputs ADSC ADSP and ADV Write Enables BWX and BWE and Global Write GW Asynchronous inputs include the Output Enable OE and the ZZ pin Addresses and chip enables are registered at rising edge of ...

Страница 2: ...D SLEEP CONTROL ZZ A 1 0 2 DQA DQPA BYTE WRITE REGISTER DQB DQPB BYTE WRITE REGISTER DQC DQPC BYTE WRITE REGISTER DQD DQPD BYTE WRITE REGISTER DQA DQPA BYTE WRITE DRIVER DQB DQPB BYTE WRITE DRIVER DQC DQPC BYTE WRITE DRIVER DQD DQPD BYTE WRITE DRIVER A0 A1 A ADDRESS REGISTER ADV CLK BURST COUNTER AND LOGIC CLR Q1 Q0 ADSC BW B BW A CE1 DQB DQPB WRITE REGISTER DQA DQPA WRITE REGISTER ENABLE REGISTER...

Страница 3: ... D DQP E DQP F DQP G DQP H OUTPUT REGISTERS MEMORY ARRAY OUTPUT BUFFERS E DQ A DQPA WRITE DRIVER DQ B DQPB WRITE DRIVER DQ C DQPC WRITE DRIVER DQ D DQPD WRITE DRIVER INPUT REGISTERS BYTE a WRITE DRIVER DQ E DQPE WRITE DRIVER DQ F DQPF WRITE DRIVER DQ G DQPG WRITE DRIVER DQ H DQPH WRITE DRIVER SENSE AMPS SLEEP CONTROL ZZ DQ A DQPA WRITE DRIVER DQ B DQPB WRITE DRIVER DQ C DQPC WRITE DRIVER DQ D DQPD...

Страница 4: ... 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CY7C1480V25 2M x 36 NC A A A A A 1 A 0 A A V SS V DD A A A A A A A A A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC A A CE 1 C...

Страница 5: ... 1G DQPB VDDQ VDD DQB DQB DQB NC DQB NC DQA DQA VDD VDDQ VDD VDDQ DQB VDD NC VDD DQA VDD VDDQ DQA VDDQ VDD VDD VDDQ VDD VDDQ DQA VDDQ A A VSS A A A DQB DQB DQB ZZ DQA DQA DQPA DQA A VDDQ A A0 A VSS 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R TDO NC 288M NC 144M NC NC DQPB NC DQB A CE1 NC CE3 BWB BWE A CE2 NC DQB DQB MODE NC DQB DQB NC NC NC A A VDDQ NC BWA CLK GW VSS VSS VSS VSS VDDQ VSS VDD VSS V...

Страница 6: ... DQA DQA DQA DQA DQE DQE DQE DQE DQPA DQPB DQF DQF DQF DQF NC DQA DQA DQA DQA DQPE DQE DQE DQE DQE A ADSP ADV A NC NC A A A A A A A A A A A1 A0 A A A A A A NC 144M NC 288M NC 576M GW NC NC BWSB BWSF BWSE BWSA BWSC BWSG BWSD BWSH TMS TDI TDO TCK NC NC MODE NC VSS VSS NC CLK NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS NC 1G VDD NC OE CE3 CE1 CE2 ADSC BW...

Страница 7: ...ins behave as outputs When deasserted HIGH IO pins are tri stated and act as input data pins OE is masked during the first clock of a read cycle when emerging from a deselected state ADV Input Synchronous Advance Input signal sampled on the rising edge of CLK active LOW When asserted it automatically increments the address in a burst cycle ADSP Input Synchronous Address Strobe from Processor sampl...

Страница 8: ...t and either ADSP or ADSC signals its output will tri state immediately Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise 1 ADSP is asserted LOW and 2 CE1 CE2 CE3 are all asserted active The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory...

Страница 9: ...that implements either an interleaved or linear burst sequence The interleaved burst sequence is designed specifically to support Intel Pentium applications The linear burst sequence is designed to support processors that follow a linear burst sequence The burst sequence is user selectable through the MODE input Asserting ADV LOW at clock rise automatically increments the burst counter to the next...

Страница 10: ...wn None H X X L X L X X X L H Tri State Deselect Cycle Power Down None L L X L L X X X X L H Tri State Deselect Cycle Power Down None L X H L L X X X X L H Tri State Deselect Cycle Power Down None L L X L H L X X X L H Tri State Deselect Cycle Power Down None L X H L H L X X X L H Tri State Sleep Mode Power Down None X X X H X X X X X X Tri State Read Cycle Begin Burst External L H L L L X X X L L...

Страница 11: ...tes D C A H L L L H L Write Bytes D C B H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Truth Table for Read Write The read write truth table for the CY7C1482V25 follows 5 Function GW BWE BWB BWA Read H H X X Read H L H H Write Byte A DQA and DQPA H L H L Write Byte B DQB and DQPB H L L H Write Bytes B A H L L L Write All Bytes H L L L Write All Bytes L X X X Truth Table for Re...

Страница 12: ...in a logic HIGH level Test Data In TDI The TDI ball serially inputs information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information on loading the instruction register see the TAP Controller State Diagram TDI is internally pulled up and can be unco...

Страница 13: ... control signals into the SRAM and cannot preload the IO buffers The SRAM does not implement the 1149 1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE PRELOAD rather it performs a capture of the IO ring when these instructions are executed Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this st...

Страница 14: ...n is that it shortens the boundary scan path when multiple devices are connected together on a board Reserved These instructions are not implemented but are reserved for future use Do not use these instructions TAP Timing TAP AC Switching Characteristics Over the Operating Range 9 10 Parameter Description Min Max Unit Clock tTCYC TCK Clock Cycle Time 50 ns tTF TCK Clock Frequency 20 MHz tTH TCK Cl...

Страница 15: ... VOH2 Output HIGH Voltage IOH 100 µA VDDQ 2 5V 2 1 V VDDQ 1 8V 1 6 V VOL1 Output LOW Voltage IOL 1 0 mA VDDQ 2 5V 0 4 V VOL2 Output LOW Voltage IOL 100 µA VDDQ 2 5V 0 2 V VDDQ 1 8V 0 2 V VIH Input HIGH Voltage VDDQ 2 5V 1 7 VDD 0 3 V VDDQ 1 8V 1 26 VDD 0 3 V VIL Input LOW Voltage VDDQ 2 5V 0 3 0 7 V VDDQ 1 8V 0 3 0 36 V IX Input Load Current GND VI VDDQ 5 5 µA Identification Register Definitions I...

Страница 16: ...AD 100 Captures the IO ring contents Places the boundary scan register between TDI and TDO Does not affect SRAM operation RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operations Boundary Scan Exit Order 2M x 36 Bit ...

Страница 17: ...Ball ID 1 D2 19 R8 37 C11 2 E2 20 P3 38 A11 3 F2 21 P4 39 A10 4 G2 22 P8 40 B10 5 J1 23 P9 41 A9 6 K1 24 P10 42 B9 7 L1 25 R9 43 A8 8 M1 26 R10 44 B8 9 N1 27 R11 45 A7 10 R1 28 M10 46 B7 11 R2 29 L10 47 B6 12 R3 30 K10 48 A6 13 P2 31 J10 49 B5 14 R4 32 H11 50 A4 15 P6 33 G11 51 B3 16 R6 34 F11 52 A3 17 N6 35 E11 53 A2 18 P11 36 D11 54 B2 Feedback ...

Страница 18: ...8 D2 36 W2 64 P11 92 U8 9 E1 37 T6 65 P10 93 A7 10 E2 38 V3 66 N11 94 A5 11 F1 39 V4 67 N10 95 A6 12 F2 40 U4 68 M11 96 D6 13 G1 41 W5 69 M10 97 B6 14 G2 42 V6 70 L11 98 D7 15 H1 43 W6 71 L10 99 K3 16 H2 44 U3 72 P6 100 A8 17 J1 45 U9 73 J11 101 B4 18 J2 46 V5 74 J10 102 B3 19 L1 47 U5 75 H11 103 C3 20 L2 48 U6 76 H10 104 C4 21 M1 49 W7 77 G11 105 C8 22 M2 50 V7 78 G10 106 C9 23 N1 51 U7 79 F11 10...

Страница 19: ... 3V V for 1 8V IO 1 26 VDD 0 3V V VIL Input LOW Voltage 12 for 2 5V IO 0 3 0 7 V for 1 8V IO 0 3 0 36 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 µA Input Current of MODE Input VSS 30 µA Input VDD 5 µA Input Current of ZZ Input VSS 5 µA Input VDD 30 µA IOZ Output Leakage Current GND VI VDDQ Output Disabled 5 5 µA IDD VDD Operating Supply Current VDD Max IOUT 0 mA f fMAX 1 tCYC 4 ...

Страница 20: ...ax 209 FBGA Max Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 24 63 16 3 15 2 C W ΘJC Thermal Resistance Junction to Case 2 28 2 1 1 7 C W Note 14 Tested initially and after any design or process change that may affect these parameters AC Test Loads and Waveforms OUTPUT R 1667Ω R 1583Ω 5 pF...

Страница 21: ...istics Over the Operating Range 15 16 Parameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Min Max Min Max tPOWER VDD Typical to the first access 17 1 1 1 ms Clock tCYC Clock Cycle Time 4 0 5 0 6 0 ns tCH Clock HIGH 2 0 2 0 2 4 ns tCL Clock LOW 2 0 2 0 2 4 ns Output Times tCO Data Output Valid After CLK Rise 3 0 3 0 3 4 ns tDOH Data Output Hold After CLK Rise 1 3 1 3 1 5 ns tCLZ Clock to Low...

Страница 22: ...CLZ tDOH tCO ADV tOEHZ tCO Single READ BURST READ tOEV tOELZ tCHZ ADV suspends burst Burst wraps around to its initial state tADVH tADVS tWEH tWES tADH tADS Q A2 Q A2 1 Q A2 2 Q A1 Q A2 Q A2 1 Q A2 3 A2 A3 Deselect cycle Burst continued with new base address DON T CARE UNDEFINED Note 21 On this diagram when CE is LOW CE1 is LOW CE2 is HIGH and CE3 is LOW When CE is HIGH CE1 is HIGH or CE2 is LOW o...

Страница 23: ...URST READ BURST WRITE D A2 D A2 1 D A2 1 D A1 D A3 D A3 1 D A3 2 D A2 3 A2 A3 Data In D Extended BURST WRITE D A2 2 Single WRITE tADH tADS tADH tADS t OEHZ t ADVH t ADVS tWEH tWES tDH tDS GW tWEH tWES Byte write signals are ignored for first cycle when ADSP initiates burst ADSC extends burst ADV suspends burst DON T CARE UNDEFINED Note 22 Full width write can be initiated by either GW LOW or by GW...

Страница 24: ...AS A2 tCEH tCES Data Out Q High Z ADV Single WRITE D A3 A4 A5 A6 D A5 D A6 Data In D BURST READ Back to Back READs High Z Q A2 Q A1 Q A4 Q A4 1 Q A4 2 tWEH tWES Q A4 3 tOEHZ tDH tDS tOELZ tCLZ tCO Back to Back WRITEs A1 DON T CARE UNDEFINED A3 BWE BWX Notes 23 The data bus Q remains in high Z following a write cycle unless a new read access is initiated by ADSP or ADSC 24 GW is HIGH Feedback ...

Страница 25: ...inued tZZ I SUPPLY CLK ZZ tZZREC ALL INPUTS except ZZ DON T CARE I DDZZ tZZI tRZZI Outputs Q High Z DESELECT or READ Only Notes 25 Device must be deselected when entering ZZ mode See Truth Table on page 10 for all possible signal conditions to deselect the device 26 DQs are in high Z when exiting ZZ sleep mode Feedback ...

Страница 26: ...CY7C1480V25 167BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1482V25 167BZXI CY7C1486V25 167BGI 51 85167 209 ball Fine Pitch Ball Grid Array 14 22 1 76 mm CY7C1486V25 167BGXI 209 ball Fine Pitch Ball Grid Array 14 22 1 76 mm Pb Free 200 CY7C1480V25 200AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1482V25 200AXC CY7C1480V25 200BZC ...

Страница 27: ...7C1480V25 250AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1482V25 250AXI CY7C1480V25 250BZI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1482V25 250BZI CY7C1480V25 250BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Lead Free CY7C1482V25 250BZXI CY7C1486V25 250BGI 51 85167 209 ball Fine Pitch Ball Grid Array 14 22 1 76 mm...

Страница 28: ...SION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 3 DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 00 0 20 1 40 0 05 12 1 1 60 MAX 0 05 MIN 0 60 0 15 0 MIN 0 25 0 7 8X STAND OFF R 0 08 MIN TYP 0 20 MAX 0 15 MAX 0 20 MAX R 0 08 MIN 0 20 MAX 14 00 0 10 16 00 0 20 0 10 SEE DETAIL A DETAIL A 1 100 30 0 5 1 3 51 8...

Страница 29: ... A 1 PIN 1 CORNER 17 00 0 10 15 00 0 10 7 00 1 00 Ø0 45 0 05 165X Ø0 25 M C A B Ø0 05 M C B A 0 15 4X 0 35 1 40 MAX SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11 11 10 9 8 6 7 5 4 3 2 1 P R P R K M N L J H G F E D C B A C 1 00 5 00 0 36 0 05 0 10 51 85165 A Feedback ...

Страница 30: ... pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in ...

Страница 31: ... TQFP 165 FBGA and 209 BGA Packages Added comment of Lead free BG packages availability below the Ordering Information D 323039 See ECN PCI Unshaded 200 and 167 MHz speed bin in the AC DC Table and Selection Guide Address expansion pins balls in the pinouts for all packages are modified as per JEDEC standard Added Address Expansion pins in the Pin Definitions Table Added Truth Table and Note 7 for...

Страница 32: ...209 Ball FBGA pinout Corrected the ball name H9 to VSS from VSSQ H 1026720 See ECN VKN KKVTMP Added footnote 2 related to VSSQ Document Title CY7C1480V25 CY7C1482V25 CY7C1486V25 72 Mbit 2M x 36 4M x 18 1M x 72 Pipelined Sync SRAM Document Number 38 05282 REV ECN NO Issue Date Orig of Change Description of Change Feedback ...

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