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CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

Document #: 001-15029 Rev. *B

Page 9 of 32

Functional Overview

The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33
are synchronous flow through burst SRAMs designed
specifically to eliminate wait states during write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
Clock Enable input signal (CEN). If CEN is HIGH, the clock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. Maximum
access delay from the clock rise (t

CDV

) is 6.5 ns (133 MHz

device).

Accesses may be initiated by asserting all three Chip Enables
(CE

, CE

) active at the rising edge of the clock. If (CEN)

is active LOW and ADV/LD is asserted LOW, the address
presented to the device is latched. The access can either be a
read or write operation, depending on the status of the Write
Enable (WE). Byte Write Select (BW

) can be used to conduct

Byte Write operations.

Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self timed write
circuitry.

Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device is deselected to load a new
address for the next operation.

Single Read Accesses

A read access is initiated when these conditions are satisfied at
clock rise:

■

CEN is asserted LOW

■

, CE

, and CE

are ALL asserted active

■

WE is deasserted HIGH

■

ADV/LD is asserted LOW

The address presented to the address inputs is latched into the
Address Register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 6.5 ns (133 MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW to drive out the
requested data. On the subsequent clock, another operation
(read/write/deselect) can be initiated. When the SRAM is
deselected at clock rise by one of the chip enable signals, output
is tri-stated immediately.

Burst Read Accesses

The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33
have an on-chip burst counter that enables the user to supply a
single address and conduct up to four reads without reasserting
the address inputs. ADV/LD must be driven LOW to load a new
address into the SRAM, as described in the Single Read Access
section. The sequence of the burst counter is determined by the
MODE input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both burst
counters use A0 and A1 in the burst sequence, and wrap around
when incremented sufficiently. A HIGH input on ADV/LD
increments the internal burst counter regardless of the state of
chip enable inputs or WE. WE is latched at the beginning of a
burst cycle. Therefore, the type of access (read or write) is
maintained throughout the burst sequence.

TDO

JTAG serial

output

Synchronous

Serial Data-Out to the JTAG Circuit

. Delivers data on the negative edge of TCK. If the JTAG

feature is not used, this pin must be left unconnected. This pin is not available on TQFP
packages.

TDI

JTAG serial input

Synchronous

Serial Data-In to the JTAG Circuit

. Sampled on the rising edge of TCK. If the JTAG feature is