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CY7C1360C
CY7C1362C

Document #: 38-05540 Rev. *H

Page 27 of 31

250

CY7C1360C-250AXC

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

(3 Chip Enable)

Commercial

CY7C1362C-250AXC

CY7C1360C-250AJXC

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

(2 Chip Enable)

CY7C1362C-250AJXC

CY7C1360C-250BGC

51-85115

119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1362C-250BGC

CY7C1360C-250BGXC

51-85115

119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1362C-250BGXC

CY7C1360C-250BZC

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1362C-250BZC

CY7C1360C-250BZXC

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

CY7C1362C-250BZXC

CY7C1360C-250AXI

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

(3 Chip Enable)

Industrial

CY7C1362C-250AXI

CY7C1360C-250AJXI

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

(2 Chip Enable)

CY7C1362C-250AJXI

CY7C1360C-250BGI

51-85115

119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1362C-250BGI

CY7C1360C-250BGXI

51-85115

119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1362C-250BGXI

CY7C1360C-250BZI

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1362C-250BZI

CY7C1360C-250BZXI

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

CY7C1362C-250BZXI

Ordering Information

(continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit

www.cypress.com

for actual products offered.

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Содержание CY7C1360C

Страница 1: ...2 Burst Control inputs ADSC ADSP and ADV Write Enables BWX and BWE and Global Write GW Asynchronous inputs include the Output Enable OE and the ZZ pin Addresses and chip enables are registered at ris...

Страница 2: ...DSC MODE BWE GW CE1 CE2 CE3 OE ENABLE REGISTER OUTPUT REGISTERS SENSE AMPS OUTPUT BUFFERS E PIPELINED ENABLE INPUT REGISTERS A0 A1 A BWB BWC BWD BWA MEMORY ARRAY DQs DQPA DQPB DQPC DQPD SLEEP CONTROL...

Страница 3: ...2 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 MODE CY7C1360C 256K X 36 NC A A A A A 1 A 0 NC 72M NC 36M V SS V DD NC 18M A A A A A A A A A NC NC VDDQ...

Страница 4: ...63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 MODE CY7C1360C 256K X 36 NC A A A A A 1 A 0 NC 72M NC 36M V SS V DD A A A A A A A A NC NC VDDQ VSSQ...

Страница 5: ...C NC CE1 OE ADV GW VSS VSS VSS VSS VSS VSS VSS VSS DQPA MODE DQPD DQPB BWB BWC NC VDD NC BWA NC BWE BWD ZZ 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R T U VDDQ NC 288M NC 144M NC DQB DQB DQB DQB A A A...

Страница 6: ...DQB NC DQB NC DQA DQA VDD VDDQ VDD VDDQ DQB VDD NC VDD DQA VDD VDDQ DQA VDDQ VDD VDD VDDQ VDD VDDQ DQA VDDQ A A VSS A A A DQB DQB DQB ZZ DQA DQA DQPA DQA A VDDQ A CY7C1362C 512K x 18 A0 A VSS 2 3 4 5...

Страница 7: ...of a read cycle when emerging from a deselected state ADV Input Synchronous Advance Input signal sampled on the rising edge of CLK active LOW When asserted it automatically increments the address in a...

Страница 8: ...he following conditions are satisfied at clock rise 1 ADSP is asserted LOW and 2 CE1 CE2 CE3 2 are all asserted active The address presented to A is loaded into the address register and the address ad...

Страница 9: ...ar Burst Address Table MODE GND First Address A1 A0 Second Address A1 A0 Third Address A1 A0 Fourth Address A1 A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Par...

Страница 10: ...Burst Current X X X L H H H L X L H D WRITE Cycle Suspend Burst Current H X X L X H H L X L H D Partial Truth Table for Read Write 5 9 Function CY7C1360C GW BWE BWD BWC BWB BWA Read H H X X X X Read H...

Страница 11: ...e TAP controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Test MODE SELECT TMS The TMS input is used to give commands to the TAP controller...

Страница 12: ...rresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specifi...

Страница 13: ...Repeatable results may not be possible To guarantee that the boundary scan register will capture the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller...

Страница 14: ...Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns Set up Times tTMSS TMS Set up to TCK Clock Rise 5 ns tTDIS TDI Set up to TCK Clock Rise 5 ns tCS Capture Set up to TCK Rise 5 ns Hold Times tTMSH TM...

Страница 15: ...Description Conditions Min Max Unit Scan Register Sizes Register Name Bit Size x36 Bit Size x18 Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order 119 ball BGA package 71 71 Boundary Scan Order...

Страница 16: ...50 L1 DQB 15 D11 DQB 51 K1 DQD 15 D11 DQA 51 K1 DQB 16 E11 DQB 52 J1 DQD 16 E11 DQA 52 J1 DQB 17 F11 DQB 53 Internal Internal 17 F11 DQA 53 Internal Internal 18 G11 DQB 54 G2 DQC 18 G11 DQA 54 G2 DQB...

Страница 17: ...0 M2 DQB 15 E7 DQB 51 L1 DQD 15 E7 DQA 51 L1 DQB 16 F6 DQB 52 K2 DQD 16 F6 DQA 52 K2 DQB 17 G7 DQB 53 Internal Internal 17 G7 DQA 53 Internal Internal 18 H6 DQB 54 H1 DQC 18 H6 DQA 54 H1 DQB 19 T7 ZZ...

Страница 18: ...for 2 5V I O 1 7 VDD 0 3V V VIL Input LOW Voltage 14 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input Current of MODE Input VSS 30 A I...

Страница 19: ...ion to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 29 41 34 1 16 8 C W JC Thermal Resistance Junction to Case 6 13 14 0 3 C W AC...

Страница 20: ...Hold Times tAH Address Hold after CLK Rise 0 4 0 5 0 5 ns tADH ADSP ADSC Hold after CLK Rise 0 4 0 5 0 5 ns tADVH ADV Hold after CLK Rise 0 4 0 5 0 5 ns tWEH GW BWE BWX Hold after CLK Rise 0 4 0 5 0 5...

Страница 21: ...LOW or CE3 is HIGH tCYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE tAH tAS A1 tCEH tCES GW BWE BWx Data Out Q High Z tCLZ tDOH tCO ADV tOEHZ tCO Single READ BURST READ tOEV tOELZ tCHZ ADV suspe...

Страница 22: ...ADH tADS ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES BWE BWX Data Out Q High Z ADV BURST READ BURST WRITE D A2 D A2 1 D A2 1 D A1 D A3 D A3 1 D A3 2 D A2 3 A2 A3 Data In D Extended BURST WRITE D A2 2...

Страница 23: ...nitiated by ADSP or ADSC 26 GW is HIGH Switching Waveforms continued tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A2 tCEH tCES BWE BWX Data Out Q High Z ADV Single WRITE D A3 A4 A5 A6 D...

Страница 24: ...when entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device 28 DQs are in High Z when exiting ZZ sleep mode Switching Waveforms continued t ZZ I SUPPLY...

Страница 25: ...rid Array 14 x 22 x 2 4 mm Lead Free CY7C1362C 166BGXC CY7C1360C 166BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1362C 166BZC CY7C1360C 166BZXC 51 85180 165 ball Fine Pitch Ba...

Страница 26: ...Lead Free CY7C1362C 200BZXC CY7C1360C 200AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free 3 Chip Enable Industrial CY7C1362C 200AXI CY7C1360C 200AJXI 51 85050 100 pin Thin Quad Flat...

Страница 27: ...Lead Free CY7C1362C 250BZXC CY7C1360C 250AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free 3 Chip Enable Industrial CY7C1362C 250AXI CY7C1360C 250AJXI 51 85050 100 pin Thin Quad Flat...

Страница 28: ...N MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 00 0 20 1 40 0 05 12 1 1 60 MAX 0 05 MIN 0 60 0 15 0 MIN 0 25 0 7 8X STAND OFF R 0 0...

Страница 29: ...J U P N M T R 12 00 19 50 30 TYP 2 40 MAX A1 CORNER 0 70 REF U T R P N M L K J H G F E D C A B 2 1 4 3 6 5 7 1 00 3X REF 7 62 22 00 0 20 14 00 0 20 1 27 0 60 0 10 C 0 15 C B A 0 15 4X 0 05 M C 0 75 0...

Страница 30: ...tion PowerPC is a trademark of IBM Corporation All product and company names mentioned in this document are the trademarks of their respective holders Package Diagrams continued A 1 PIN 1 CORNER 15 00...

Страница 31: ...as per JEDEC Standard Removed comment of Lead free BG and BZ packages availability D 332879 See ECN PCI Unshaded 200 and 166 MHz speed bins in the AC DC Table and Selection Guide Added Address Expans...

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