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CY7C1350G

Document #: 38-05524 Rev. *F

Page 15 of 15

Document History Page

Document Title: CY7C1350G 4-Mbit (128K x 36) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05524

REV.

ECN NO.

Issue
Date

Orig. of
Change Description of Change

**

224380

See ECN

RKF

New data sheet

*A

276690

See ECN

VBL

Changed TQFP pkg to lead-free TQFP in Ordering Info section
Added comment of BG lead-free package availability

*B

332895

See ECN

SYT

Converted from Preliminary to Final
Removed 225 MHz and 100 MHz speed grades
Address Expansion balls in the pinouts for 119 BGA Package was modified as per
JEDEC standards
Modified V

OL,

V

OH

test conditions

Replaced TBDs for

Θ

JA

and

Θ

JC

to their respective values on the Thermal Resistance

table
Changed the package name for 100 TQFP from A100RA to A101
Removed comment on the availability of BG lead-free package
Updated Ordering Information by removing Shaded Parts

*C

351194

See ECN

PCI

Updated Ordering Information Table

*D

419264

See ECN

RXU

Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Modified test condition from V

DDQ

< V

DD

to V

DDQ

< V

DD

Modified test condition from V

IH

< V

DD

to

V

IH

<

V

DD

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering Information
table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information

*E

419705

See ECN

RXU

Added 100 MHz speed grade

*F

480368

See ECN

VKN

Added the Maximum Rating for Supply Voltage on V

DDQ

Relative to GND.

Updated the Ordering Information table.

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Содержание CY7C1350G

Страница 1: ...ent Write Read transitions All synchronous inputs pass through input registers controlled by the rising edge of the clock All data outputs pass through output registers controlled by the rising edge of the clock The clock input is qualified by the Clock Enable CEN signal which when deasserted suspends operation and extends the previous clock cycle Maximum access delay from the clock rise is 2 6 ns...

Страница 2: ...A DQA DQA VSS VDDQ DQA DQA DQPA DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD A A CE 1 CE 2 BW D BW C BW B BW A CE 3 V DD V SS CLK WE CEN OE A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 ...

Страница 3: ...is advanced When LOW a new address can be loaded into the device for an access After being deselected ADV LD should be driven LOW in order to load a new address CLK Input Clock Clock Input Used to capture all synchronous inputs to the device CLK is qualified with CEN CLK is only recognized if CEN is active LOW CE1 Input Synchronous Chip Enable 1 Input active LOW Sampled on the rising edge of CLK U...

Страница 4: ... chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs ADV LD must be driven LOW in order to load a new address into the SRAM as described in the Single Read Access section above The sequence of the burst counter is determined by the MODE input signal A LOW input on MODE selects a linear burst mode a HIGH ...

Страница 5: ... in order to write the correct bytes of data Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM in a power conservation sleep mode Two clock cycles are required to enter into or exit from this sleep mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guarant...

Страница 6: ... H Write Bytes D A L L H H L Write Bytes D B L L H L H Write Bytes D B A L L H L L Write Bytes D C L L L H H Write Bytes D C A L L L H L Write Bytes D C B L L L L H Write All Bytes L L L L L ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Snooze mode standby current ZZ VDD 0 2V 40 mA tZZS Device operation to ZZ ZZ VDD 0 2V 2tCYC ns tZZREC ZZ recovery tim...

Страница 7: ...or 2 5V I O IOL 1 0 mA 0 4 V VIH Input HIGH Voltage 10 VDDQ 3 3V 2 0 VDD 0 3V V VDDQ 2 5V 1 7 VDD 0 3V V VIL Input LOW Voltage 10 VDDQ 3 3V 0 3 0 8 V VDDQ 2 5V 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 µA Input Current of MODE Input VSS 30 µA Input VDD 5 µA Input Current of ZZ Input VSS 5 µA Input VDD 30 µA IOZ Output Leakage Current GND VI VDDQ Output Disabled 5 5 µA I...

Страница 8: ...er Description Test Conditions 100 TQFP Package 119 BGA Package Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 30 32 34 1 C W ΘJC Thermal Resistance Junction to Case 6 85 14 0 C W Electrical Characteristics Over the Operating Range 10 11 continued Parameter Description Test Conditions Min Ma...

Страница 9: ...K Rise 1 2 1 2 1 5 1 5 1 5 ns Hold Times tAH Address Hold After CLK Rise 0 3 0 5 0 5 0 5 0 5 ns tALH ADV LD Hold after CLK Rise 0 3 0 5 0 5 0 5 0 5 ns tWEH GW BWX Hold After CLK Rise 0 3 0 5 0 5 0 5 0 5 ns tCENH CEN Hold After CLK Rise 0 3 0 5 0 5 0 5 0 5 ns tDH Data Input Hold After CLK Rise 0 3 0 5 0 5 0 5 0 5 ns tCEH Chip Enable Hold After CLK Rise 0 3 0 5 0 5 0 5 0 5 ns Notes 13 This part has ...

Страница 10: ...nce is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional WRITE D A1 1 2 3 4 5 6 7 8 9 CLK t CYC tCL tCH 10 CE tCEH tCES WE CEN tCENH tCENS BW A D ADV LD tAH tAS ADDRESS A1 A2 A3 A4 A5 A6 A7 tDH tDS Data In Out DQ tCLZ D A1 D A2 D A5 Q A4 Q A3 D A2 1 tDOH tCHZ tCO WRITE D A2 BURST WRITE D A2 1 READ Q A3 READ Q A4 BURST READ Q A4 1 WRITE D A5 READ Q A6 WRITE D...

Страница 11: ... description table for all possible signal conditions to deselect the device 24 DQs are in high Z when exiting ZZ sleep mode Switching Waveforms continued READ Q A3 4 5 6 7 8 9 10 CLK CE WE CEN BW A D ADV LD ADDRESS A3 A4 A5 D A4 Data In Out DQ A1 Q A5 WRITE D A4 STALL WRITE D A1 1 2 3 READ Q A2 STALL NOP READ Q A5 DESELECT CONTINUE DESELECT DON T CARE UNDEFINED tCHZ A2 D A1 Q A2 Q A3 tZZ I SUPPLY...

Страница 12: ...2 4 mm Lead Free 166 CY7C1350G 166AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1350G 166BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1350G 166BGXC 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1350G 166AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1350G 166BGI 51 85115 119 ball Ball Grid Array 14 x 2...

Страница 13: ...SIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 00 0 20 1 40 0 05 12 1 1 60 MAX 0 05 MIN 0 60 0 15 0 MIN 0 25 0 7 8X STAND OFF R 0 08 MIN TYP 0 20 MAX 0 15 MAX 0 20 MAX R 0 08 MIN 0 20 MAX 14 00 0 10 16 00 0 20 0 10 SEE DETAIL A DETAIL A 1 100 30 31 50 51 80 81 GAUGE PLANE 1 00 REF 0 20 MIN SEATING PLANE 100 Pin TQFP 14 x 2...

Страница 14: ...ure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges ZBT is a trademark of Integrated Device Technology Inc NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation All produ...

Страница 15: ...ge name for 100 TQFP from A100RA to A101 Removed comment on the availability of BG lead free package Updated Ordering Information by removing Shaded Parts C 351194 See ECN PCI Updated Ordering Information Table D 419264 See ECN RXU Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Modified test cond...

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