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Cypress Semiconductor CY7C1344H, Техническое описание

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CY7C1344H

Document #: 001-00211 Rev. *B

Page 12 of 15

Read/Write Timing

[16, 18, 19]

Notes: 

18. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.
19. GW is HIGH.

Timing Diagrams

 (continued)

tCYC

t

CL

CLK

tADH

tADS

ADDRESS

t

CH

tAH

tAS

A2

tCEH

tCES

Single WRITE

D(A3)

A3

A4

BURST READ

Back-to-Back READs

High-Z

Q(A2)

Q(A4)

Q(A4+1)

Q(A4+2)

Q(A4+3)

t

WEH

t

WES

t

OEHZ

tDH

tDS

tCDV

tOELZ

A1

A5

A6

D(A5)

D(A6)

Q(A1)

Back-to-Back

WRITEs

DON’T CARE

UNDEFINED

ADSP

ADSC

 BWE, BW

[A:D]

CE

ADV

OE

Data In (D)

Data Out (Q)

[+] Feedback 

Содержание CY7C1344H

Страница 1: ...Write GW Asynchronous inputs include the Output Enable OE and the ZZ pin The CY7C1344H allows either interleaved or linear burst sequences selected by the MODE input pin A HIGH selects an interleaved...

Страница 2: ...Q VDDQ DQA DQA DQPA DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD A A CE 1 CE 2 BW D BW C BW B BW A CE 3 V DD V SS CLK...

Страница 3: ...ted state ADV Input Synchronous Advance Input signal sampled on the rising edge of CLK When asserted it automatically incre ments the address in a burst cycle ADSP Input Synchronous Address Strobe fro...

Страница 4: ...te Writes BWA controls DQA and BWB controls DQB BWC controls DQC and BWD controls DQD All I Os are tri stated during a Byte Write Since this is a common I O device the asynchronous OE input signal mus...

Страница 5: ...e Burst Next H X X L X H L H L L H Q Read Cycle Continue Burst Next H X X L X H L H H L H Tri State Write Cycle Continue Burst Next X X X L H H L L X L H D Write Cycle Continue Burst Next H X X L X H...

Страница 6: ...H H Write Bytes C A DQPC DQPA H L H L H L Write Bytes C B DQPC DQPB H L H L L H Write Bytes C B A DQPC DQPB DQPA H L H L L L Write Byte D DQPD H L L H H H Write Bytes D A DQPD DQPA H L L H H L Write B...

Страница 7: ...0 3V V for 2 5V I O 1 7 VDD 0 3V VIL Input LOW Voltage 7 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input Current of MODE Input VSS 30 A...

Страница 8: ...ollow standard test methods and procedures for measuring thermal impedance per EIA JESD51 30 32 C W JC Thermal Resistance Junction to Case 6 85 C W AC Test Loads and Waveforms Note 9 Tested initially...

Страница 9: ...0 5 ns tADH ADSP ADSC Hold after CLK Rise 0 5 0 5 ns tWEH GW BWE BW A D Hold after CLK Rise 0 5 0 5 ns tADVH ADV Hold after CLK Rise 0 5 0 5 ns tDH Data Input Hold after CLK Rise 0 5 0 5 ns tCEH Chip...

Страница 10: ...CE2 is LOW or CE3 is HIGH tCYC tCL CLK tADH tADS ADDRESS t CH tAH tAS A1 tCEH tCES Data Out Q High Z tCLZ tDOH tCDV tOEHZ tCDV Single READ BURST READ tOEV tOELZ tCHZ Burst wraps around to its initial...

Страница 11: ...ESS t CH tAH tAS A1 tCEH tCES High Z BURST READ BURST WRITE D A2 D A2 1 D A2 1 D A1 D A3 D A3 1 D A3 2 D A2 3 A2 A3 Extended BURST WRITE D A2 2 Single WRITE tADH tADS tADH tADS t OEHZ tADVH tADVS tWEH...

Страница 12: ...cle is performed 19 GW is HIGH Timing Diagrams continued tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A2 tCEH tCES Single WRITE D A3 A3 A4 BURST READ Back to Back READs High Z Q A2 Q A4 Q A4 1 Q A4 2...

Страница 13: ...hen entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device 21 DQs are in High Z when exiting ZZ sleep mode Timing Diagrams continued tZZ I SUPPLY CLK Z...

Страница 14: ...be the trademarks of their respective holders Ordering Information Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypres...

Страница 15: ...rporation on Page 1 from 3901 North First Street to 198 Champion Court Changed Three State to Tri State Modified Input Load to Input Leakage Current except ZZ and MODE in the Electrical Characteristic...

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