background image

CY7C1215H

Document #: 38-05666 Rev. *B

Page 14 of 15

© Cypress Semiconductor Corporation, 2006. The information contained herein is subject  to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark
of IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders.

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit 

www.cypress.com 

for actual products offered.

Speed

(MHz)

Ordering Code

Package
Diagram

Package Type

Operating

Range

100

CY7C1215H-100AXC

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

CY7C1215H-100AXI

Industrial

133

CY7C1215H-133AXC

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

CY7C1215H-133AXI

Industrial

Package Diagram 

 

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

3. DIMENSIONS IN MILLIMETERS

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

0.30±0.08

0.65

20.00±0.10

22.00±0.20

1.40±0.05

12°±1°

1.60 MAX.

0.05 MIN.

0.60±0.15

0° MIN.

0.25

0°-7°

(8X)

STAND-OFF

R 0.08 MIN.

TYP.

0.20 MAX.

0.15 MAX.

0.20 MAX.

R 0.08 MIN.

0.20 MAX.

14.00±0.10

16.00±0.20

0.10

SEE DETAIL

A

DETAIL

A

1

100

30

31

50

51

80

81

GAUGE PLANE

1.00 REF.

0.20 MIN.

SEATING PLANE

100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)

51-85050-*B

[+] Feedback 

Содержание CY7C1215H

Страница 1: ...nous inputs include the Output Enable OE and the ZZ pin Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC ar...

Страница 2: ...Q VDDQ DQA DQA NC NC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD NC A A CE 1 CE 2 BW D BW C BW B BW A CE 3 V DD V SS CLK GW BW...

Страница 3: ...as input data pins OE is masked during the first clock of a Read cycle when emerging from a deselected state ADV Input Synchronous Advance Input signal sampled on the rising edge of CLK active LOW Wh...

Страница 4: ...esented to the DQ inputs is written into the corre sponding address location in the memory array If GW is HIGH then the Write operation is controlled by BWE and BW A D signals The CY7C1215H provides B...

Страница 5: ...ad Continue Read Next L H X X X H L H Tri State Read Continue Read Next L H X X X H L L DQ Read Suspend Read Current L X X X H H H H Tri State Read Suspend Read Current L X X X H H H L DQ Read Suspend...

Страница 6: ...te Byte A DQA H L H H H L Write Byte B DQB H L H H L H Write Bytes B A H L H H L L Write Byte C DQC H L H L H H Write Bytes C A H L H L H L Write Bytes C B H L H L L H Write Bytes C B A H L H L L L Wr...

Страница 7: ...ge 7 for 3 3V I O 2 0 VDD 0 3V V for 2 5V I O 1 7 VDD 0 3V V VIL Input LOW Voltage 7 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input C...

Страница 8: ...llow standard test methods and procedures for measuring thermal impedance per EIA JESD51 30 32 C W JC Thermal Resistance Junction to Case 6 85 C W AC Test Loads and Waveforms Note 9 Tested initially a...

Страница 9: ...se 0 5 0 5 ns tADH ADSP ADSC Hold after CLK Rise 0 5 0 5 ns tADVH ADV Hold after CLK Rise 0 5 0 5 ns tWEH GW BWE BW A D Hold after CLK Rise 0 5 0 5 ns tDH Data Input Hold after CLK Rise 0 5 0 5 ns tCE...

Страница 10: ...CE3 is HIGH tCYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE tAH tAS A1 tCEH tCES GW BWE BW A D Data Out Q High Z tCLZ tDOH tCO ADV tOEHZ tCO Single READ BURST READ tOEV tOELZ tCHZ ADV suspends...

Страница 11: ...ADS ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES BWE BW A D Data Out Q High Z ADV BURST READ BURST WRITE D A2 D A2 1 D A2 1 D A1 D A3 D A3 1 D A3 2 D A2 3 A2 A3 Data In D Extended BURST WRITE D A2 2 Si...

Страница 12: ...e is performed 19 GW is HIGH Switching Waveforms continued tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A2 tCEH tCES BWE BW A D Data Out Q High Z ADV Single WRITE D A3 A4 A5 A6 D A5 D A6...

Страница 13: ...entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device 21 DQs are in High Z when exiting ZZ sleep mode Switching Waveforms continued t ZZ I SUPPLY CLK...

Страница 14: ...ed trademark of IBM Corporation All product and company names mentioned in this document may be trademarks of their respective holders Ordering Information Not all of the speed package and temperature...

Страница 15: ...poration on Page 1 from 3901 North First Street to 198 Champion Court Added 2 5VI O option Changed Three State to Tri State Included Maximum Ratings for VDDQ relative to GND Modified Input Load to Inp...

Отзывы: