Cypress Semiconductor CY7C1141V18 Скачать руководство пользователя страница 18

Страница: 18 / 28

CY7C1141V18, CY7C1156V18
CY7C1143V18, CY7C1145V18

Document Number: 001-06583 Rev. *D

Page 18 of 28

Identification Register Definitions

Instruction Field

Value

Description

CY7C1141V18

CY7C1156V18

CY7C1143V18

CY7C1145V18

Revision Number
(31:29)

000

Version number.

Cypress Device ID
(28:12)

11010010101000101 11010010101001101 11010010101010101 11010010101100101 Defines the type of

SRAM.

Cypress JEDEC ID
(11:1)

00000110100

Enables unique
identification of
SRAM vendor.

ID Register
Presence (0)

Indicates the
presence of an ID
register.

Scan Register Sizes

Register Name

Bit Size

Instruction

Bypass

Boundary Scan

107

Instruction Codes

Instruction

Code

Description

EXTEST

000

Captures the input and output ring contents.

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.

SAMPLE Z

010

Captures the input and output contents. Places the boundary scan register between
TDI and TDO. This forces all SRAM output drivers to a High-Z state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

100

Captures the input and output ring contents. Places the boundary scan register
between TDI and TDO. This operation does not affect the SRAM operation.

RESERVED

101

Do not use: this instruction is reserved for future use.

RESERVED

110

Do not use: this instruction is reserved for future use.

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect
SRAM operation.

[+] Feedback

Содержание CY7C1141V18

Страница 1: ...of two separate ports to access the memory array The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations QDR II ar...

Страница 2: ...Reg Reg Reg 16 19 8 32 8 NWS 1 0 VREF Write Add Decode Write Reg 16 A 18 0 19 512K x 8 Array 512K x 8 Array 512K x 8 Array Write Reg Write Reg Write Reg 8 CQ CQ DOFF QVLD 512K x 9 Array CLK A 18 0 Gen...

Страница 3: ...Reg 36 18 18 72 18 BWS 1 0 VREF Write Add Decode Write Reg 36 A 17 0 18 256K x 18 Array 256K x 18 Array 256K x 18 Array Write Reg Write Reg Write Reg 18 CQ CQ DOFF QVLD 128K x 36 Array CLK A 16 0 Gen...

Страница 4: ...C VSS NC Q2 NC NC NC VREF NC NC VDDQ NC VDDQ NC NC VDDQ VDDQ VDDQ D1 VDDQ NC Q1 NC VDDQ VDDQ NC VSS NC D0 NC TDI TMS VSS A NC A NC D2 NC ZQ NC Q0 NC NC NC NC A NC 144M CY7C1156V18 2M x 9 2 3 4 5 6 7 1...

Страница 5: ...5 NC NC VREF NC Q3 VDDQ NC VDDQ NC Q5 VDDQ VDDQ VDDQ D4 VDDQ NC Q4 NC VDDQ VDDQ NC VSS NC D2 NC TDI TMS VSS A NC A D7 D6 NC ZQ D3 Q2 D1 Q1 D0 NC A NC CY7C1145V18 512K x 36 2 3 4 5 6 7 1 A B C D E F G...

Страница 6: ...nd write operations Internally the device is organized as 2M x 8 4 arrays each of 512K x 8 for CY7C1141V18 2M x 9 4 arrays each of 512K x 9 for CY7C1156V18 1M x 18 4 arrays each of 256K x 18 for CY7C1...

Страница 7: ...m those listed in this data sheet For normal operation connect this pin to a pull up through a 10 K or less pull up resistor The device behaves in QDR I mode when the DLL is turned off In this mode op...

Страница 8: ...rising edge of the Positive Input Clock K This enables for a seamless transition between devices without the insertion of wait states in a depth expanded memory Write Operations Write operations are i...

Страница 9: ...ks are generated by the QDR II CQ is referenced with respect to K and CQ is refer enced with respect to K These are free running clocks and are synchronized to the input clock of the QDR II The timing...

Страница 10: ...R CLKIN CLKIN D A K SRAM 4 RQ 250ohms ZQ CQ CQ Q K RPS WPS BWS D A K SRAM 1 RQ 250ohms ZQ CQ CQ Q K RPS WPS BWS RPS WPS BWS R 50ohms Vt V 2 DDQ R Notes 2 X Don t Care H Logic HIGH L Logic LOW represen...

Страница 11: ...CY7C1141V18 only the upper nibble D 7 4 is written into the device D 3 0 remains unaltered CY7C1143V18 only the upper byte D 17 9 is written into the device D 8 0 remains unaltered H L L H During the...

Страница 12: ...is written into the device D 8 0 and D 35 18 remains unaltered H L H H L H During the data portion of a write sequence only the byte D 17 9 is written into the device D 8 0 and D 35 18 remains unalter...

Страница 13: ...falling edge of TCK Instruction Register Serially load three bit instructions into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Cont...

Страница 14: ...oundary scan register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRE...

Страница 15: ...gram 11 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR SELECT IR SCAN CAPTURE IR SHIFT IR EXIT1 IR PAUSE IR EXIT2 IR UPDATE IR 1 0 1 1 0 1 0 1...

Страница 16: ...ut LOW Voltage IOL 100 A 0 2 V VIH Input HIGH Voltage 0 65 VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35 VDD V IX Input and Output Load Current GND VI VDD 5 5 A 0 0 1 2 29 30 31 Boundary Scan Register...

Страница 17: ...Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Condition The Tap Tim...

Страница 18: ...Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation...

Страница 19: ...2K 7 8P 34 11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B 92 1L 12 9P 39 11D 66 3B 93 3N 13 10M 40 9C 67 1C 94 3M 14 11N 41 9D 68 1B 95 1...

Страница 20: ...power and clock K K for 2048 cycles to lock the DLL DLL Constraints DLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tKC Var The DLL functions at...

Страница 21: ...l Impedance VDDQ 0 2 VDDQ V VOL LOW Output LOW Voltage IOL 0 1 mA Nominal Impedance VSS 0 2 V VIH Input HIGH Voltage VREF 0 1 VDDQ 0 15 V VIL Input LOW Voltage 0 15 VREF 0 1 V IX Input Leakage Current...

Страница 22: ...ient Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51 13 48 C W JC Thermal Resistance junction to case 4 15 C W AC Test Loads a...

Страница 23: ...0 2 0 2 0 2 ns tCQDOH tCQHQX Echo Clock High to Data Invalid 0 2 0 2 0 2 ns tCQH tCQHCQL Output Clock CQ CQ HIGH 25 0 88 1 03 1 15 ns tCQHCQH tCQHCQH CQ Clock Rise to CQ Clock Rise 25 rising edge to...

Страница 24: ...D A WPS RPS K K DON T CARE UNDEFINED CQ CQ tCQOH CCQO t tCQOH CCQO t tQVLD QVLD tQVLD Read Latency 2 0 Cycles CLZ t t CO tDOH tCQDOH CQD t tCHZ Q00 Q01 Q20 Q02 Q21 Q03 Q22 Q23 tCQH tCQHCQH Q Notes 30...

Страница 25: ...Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1156V18 375BZI CY7C1143V18 375BZI CY7C1145V18 375BZI CY7C1141V18 375BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Fr...

Страница 26: ...18 300BZXC CY7C1141V18 300BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1156V18 300BZI CY7C1143V18 300BZI CY7C1145V18 300BZI CY7C1141V18 300BZXI 51 85180 165 Ball Fi...

Страница 27: ...5 M C B A 0 15 4X 0 35 0 06 SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11 11 10 9 8 6 7 5 4 3 2 1 P R P R K M N L J...

Страница 28: ...LIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any...

Результаты поиска

Содержание CY7C1141V18

Отзывы:

Похожие инструкции для CY7C1141V18

Бренды по названию

Популярные бренды

Cypress Semiconductor CY7C1141V18, Техническое описание

Результаты поиска

Содержание CY7C1141V18

Отзывы:

Похожие инструкции для CY7C1141V18

Бренды по названию

Популярные бренды