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CY7C09079V/89V/99V

CY7C09179V/89V/99V

Document #: 38-06043 Rev. *C

Page 3 of 21

Pin Configurations

(continued

Figure 2. 100-Pin TQFP (Top View0 - CY7C09199V (128K x 9), CY7C09189V (64K x 9),CY7C09179V (32K x 9)

92 91 90

87 86

83 82 81

78 77

100

NC
NC
A7R
A8R

A9R

A10R

A15R

A12R

A14R

GND

CE0R

A13R

A11R

CE1R

CNTRSTR

R/WR

OER

FT/PIPER

GND

A16R

NC
NC

A7L

A8L

A9L

A10L

A15L

A12L

A14L

VCC

CE0L

A13L

A11L

CE1L

CNTRSTL

R/WL

OEL

FT/PIPEL

A16L

18
19
20
21

22
23

A6L

A5L

A4L

A3L

A1L

TEN

GND

TEN

A0R

A0L

A2L

A1R

A2R

A3R

A4R

A5R

A6R

34 35 36

39 40

43 44 45

48 49

I/O8

I/O7

I/O6

I/O5

I/0

I/O3

I/O2

GND

VCC

GND

I/O

VCC

I/O4

I/O

GND

I/O0

[8]

[9]

[+] Feedback

Содержание CY7C09079V

Страница 1: ...A typical Standby 10 A typical Fully synchronous interface for easier operation Burst counters increment addresses internally Shorten cycle times Minimize bus noise Supported in Flow Through and Pipel...

Страница 2: ...ort s burst counter is loaded with the port s Address Strobe ADS When the port s Count Enable CNTEN is asserted the address counter increments on each LOW to HIGH transition of that port s clock signa...

Страница 3: ...R A11R NC NC CE1R CNTRSTR R WR OER FT PIPER GND NC A16R 58 57 56 55 54 53 52 51 NC NC A7L A8L A9L A10L A15L A12L A14L VCC NC NC CE0L A13L A11L NC NC CE1L CNTRSTL R WL OEL FT PIPEL NC NC A16L 17 16 15...

Страница 4: ...n the address pins CE0L CE1L CE0R CE1R Chip Enable Input To select either the left or right port both CE0 AND CE1 must be asserted to their active states CE0 VIL and CE1 VIH CLKL CLKR Clock Signal Thi...

Страница 5: ...eter Description CY7C09079V 89V 99V CY7C09179V 89V 99V Unit 6 1 7 1 9 12 Min Typ Max Min Typ Max Min Typ Max Min Typ Max VOH Output HIGH Voltage VCC Min IOH 4 0 mA 2 4 2 4 2 4 2 4 V VOL Output LOW Vol...

Страница 6: ...R2 435 C 30 pF VTH 1 4V OUTPUT C 30 pF b Th venin Equivalent Load 1 c Three State Delay Load 2 R1 590 R2 435 3 3V OUTPUT C 5 pF RTH 250 Used for tCKLZ tOLZ tOHZ including scope and jig VTH 1 4V OUTPUT...

Страница 7: ...ime 3 5 4 4 4 ns tHA Address Hold Time 0 0 1 1 ns tSC Chip Enable Set Up Time 3 5 4 4 4 ns tHC Chip Enable Hold Time 0 0 1 1 ns tSW R W Set Up Time 3 5 4 4 4 ns tHW R W Hold Time 0 0 1 1 ns tSD Input...

Страница 8: ...dge 17 ADS VIL CNTEN and CNTRST VIH 18 The output is disabled high impedance state by CE0 VIH or CE1 VIL following the next rising edge of the clock 19 Addresses do not have to be accessed sequentiall...

Страница 9: ...ed tCH2 tCL2 tCYC2 tSC tHC tSW tHW tSA tHA An An 1 CLK CE0 CE1 R W ADDRESS DATAOUT OE An 2 An 3 tSC tHC tOHZ tOE tOLZ tDC tCD2 tCKLZ Qn Qn 1 Qn 2 1 Latency D3 D1 D0 D2 A0 A1 A2 A3 A4 A5 D4 A0 A1 A2 A3...

Страница 10: ...port write to flow through left port read 23 CE0 and ADS VIL CE1 CNTEN and CNTRST VIH 24 OE VIL for the right port which is being read from OE VIH for the left port which is being written to 25 It tC...

Страница 11: ...e 10 Pipelined Read to Write to Read OE VIL 19 26 27 28 Switching Waveforms continued tCYC2 tCL2 tCH2 tHC tSC tHW tSW tHA tSA tHW tSW tCD2 tCKHZ tSD tHD tCKLZ tCD2 NO OPERATION WRITE READ READ CLK CE0...

Страница 12: ...ous cycle control signals 27 CE0 and ADS VIL CE1 CNTEN and CNTRST VIH 28 During No Operation data in memory at the selected address may be corrupted and should be re written to ensure data integrity S...

Страница 13: ...orms continued tCH1 tCL1 tCYC1 tSC tHC tSW tHW tSA tHA tSW tHW tSD tHD An An 1 An 2 An 2 An 3 An 4 Dn 2 Qn Qn 1 Qn 3 tCD1 tCD1 tDC tCKHZ tCD1 tCD1 tCKLZ tDC READ NO OPERATION WRITE READ CLK CE0 CE1 AD...

Страница 14: ...Switching Waveforms continued COUNTER HOLD READ WITH COUNTER tSA tHA tSAD tHAD tSCN tHCN tCH2 tCL2 tCYC2 tSAD tHAD tSCN tHCN Qx 1 Qx Qn Qn 1 Qn 2 Qn 3 tDC tCD2 READ WITH COUNTER READ EXTERNAL ADDRESS...

Страница 15: ...CNTRST VIH 31 The Internal Address is equal to the External Address when ADS VIL and equals the counter output when ADS VIH Switching Waveforms continued tCH2 tCL2 tCYC2 An An 1 An 2 An 3 An 4 Dn 1 Dn...

Страница 16: ...sts during counter reset A READ or WRITE cycle may be coincidental with the counter reset Switching Waveforms continued tCH2 tCL2 tCYC2 CLK ADDRESS INTERNAL CNTEN ADS DATAIN ADDRESS CNTRST R W DATAOUT...

Страница 17: ...n X X X X L Dout 0 Reset Counter Reset to Address 0 An X L X H Dout n Load Address Load into Counter X An H H H Dout n Hold External Address Blocked Counter Disabled X An H L H Dout n 1 Increment Coun...

Страница 18: ...100 Pin Pb Free Thin Quad Flat Pack Industrial 128K x8 3 3V Synchronous Dual Port SRAM Speed ns Ordering Code Package Name Package Type Operating Range 6 5 1 CY7C09099V 6AC A100 100 Pin Thin Quad Flat...

Страница 19: ...l 128K x9 3 3V Synchronous Dual Port SRAM Speed ns Ordering Code Package Name Package Type Operating Range 6 5 1 CY7C09199V 6AC A100 100 Pin Thin Quad Flat Pack Commercial CY7C09199V 6AXC A100 100 Pin...

Страница 20: ...CY7C09079V 89V 99V CY7C09179V 89V 99V Document 38 06043 Rev C Page 20 of 21 Package Diagram Figure 18 100 Pin Thin Plastic Quad Flat Pack TQFP A100 51 85048 51 85048 B Feedback...

Страница 21: ...INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials describe...

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