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CY25818/19

Document #: 38-07362 Rev. *B

Page 4 of 7

Characteristics Curves

The following curves demonstrate the characteristic behavior
of the CY25818/19 when tested over a number of environ-
mental and application specific parameters. These are typical
performance curves and are not meant to replace any
parameter specified in 

Table 4

 and 

Table 5

.

 

 

Notes: 

1. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. Operation at any Absolute Maximum Rating is not implied.

Table 5. Timing Electrical Characteristics 

Vdd

 

= 3.3V ±10%, T

A

 = 0°C to +70°C and C

L

 = 15 pF (unless otherwise noted)

Parameter

Description

Conditions

Min.

Typ.

Max.

Unit

ICLKFR1

Input Frequency Range

CY25818

8

16

MHz

ICLKFR2

Input Frequency Range

CY25819

16

32

MHz

trise1

Clock Rise Time 

SSCLK and REFCLK, 0.4V to 2.4V

2.0

3.0

4.0

ns

tfall1

Clock Fall Time 

SSCLK and REFCLK, 0.4V to 2.4V

2.0

3.0

4.0

ns

CDCin

Input Clock Duty Cycle

X

IN

20

50

80

%

CDCout

Output Clock Duty Cycle

SSCLK and REFCLK @ 1.5V

45

50

55

%

CCJss

Cycle-to-Cycle Jitter

SSCLK; F

IN

 = F

OUT 

= 8–32 MHz

250

350

ps

CCJref

Cycle-to-Cycle Jitter

REFCLK; F

IN

 = F

OUT

 = 8–32 MHz

275

375

ps

2 0 0

2 1 0

2 2 0

2 3 0

2 4 0

2 5 0

2 6 0

2 7 0

2 8 0

2 9 0

3 0 0

8

1 2

1 6

2 0

2 4

2 8

3 2

F r e q u e n c y   ( M H z )

CCJ (p

s)

  R EF C L K   C Y2 5 8 18

S S C L K   C Y2 5 8 18

R EF C L K   C Y2 5 8 19

S S C L K   C Y2 5 8 19

Figure 2. CCJ (ps) vs. Frequency (MHz)

1.75

2

2.25

2.5

2.75

-40

-25

-10

5

20

35

50

65

80

95

110

125

Temp (C)

BW

 %

12 MHz

32.0 MHz

Figure 3. Bandwidth% vs. Temperature

10

11

12

13

14

15

16

17

18

19

2 0

8

12

16

2 0

2 4

2 8

3 2

F r e q u e n c y   ( M H z )

IDD(m

A

)

C Y 2 5 8 19
16   -   3 2   M H z

C Y 2 5 8 18
8   -   16   M H z

Figure 4. IDD (mA) vs. Frequency (MHz)

1.8

1.9

2

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3

3.1

2.8

2.9

3

3.1

3.2

3.3

3.4

3.5

3.6

3.7

VDD (volts)

BW

 (

%

)

CY25819@32 MHz

[email protected] MHz

Figure 5. Bandwidth% vs. Vdd

[+] Feedback 

Содержание CY25818

Страница 1: ...3 mW typ 32 MHz Low cycle to cycle jitter SSCLK 250 ps typ REFOUT 275 ps typ Available in 8 pin 150 mil SOIC package Applications Printers and MFPs LCD panels and notebook PCs Digital copiers PDAs Aut...

Страница 2: ...versions Refer to the CY25568 CY25811 CY25812 and CY25814 products for other functions such as clock multiplication of 1 2 or 4 to generate a wide range of Spread Spectrum output clocks from 4 to 128...

Страница 3: ...iven by the following formula fmod fIN DR where fmod is the Modulation Rate fIN is the Input Frequency and DR is the Divider Ratio as given in Table 3 Maximum Ratings 1 2 Supply Voltage Vdd 5 5V Input...

Страница 4: ...CLK and REFCLK 0 4V to 2 4V 2 0 3 0 4 0 ns tfall1 Clock Fall Time SSCLK and REFCLK 0 4V to 2 4V 2 0 3 0 4 0 ns CDCin Input Clock Duty Cycle XIN 20 50 80 CDCout Output Clock Duty Cycle SSCLK and REFCLK...

Страница 5: ...cs This results in additional EMI reduction in electronic systems Application Schematic Notes 3 XIN 16 0 MHz S0 1 SSCLK 16 0 MHz BW 2 14 4 Xin 32 0MHz S0 1 SSCLK 32 0 MHz BW 2 15 Figure 6 CY25818 Spre...

Страница 6: ...awing and Dimensions All product and company names mentioned in this document may be the trademarks of their respective holders Ordering Information Part Number Package Type Product Flow CY25818SC 8 p...

Страница 7: ...18 19 Spread Spectrum Clock Generator Document Number 38 07362 REV ECN NO Issue Date Orig of Change Description of Change 112462 03 21 02 OXC New Data Sheet A 122701 12 28 02 RBI Added power up requir...

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