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CPCI-824 User’s Manual

A-1

Revision 1.0, January 2006

APPENDIX A

PMC MODULE INTERFACE

A.1

INTRODUCTION

The PMC Module Interface allows PCI devices to be connected to the Local PCI interface of the CPCI-
824 host. The IEEE STD P1386.1, PCI Mezzanine Card (PMC), provides for one set of clocking and
arbitration signals per PMC Module. Cyclone Microsystems has expanded this to two sets per PMC
Module on the CPCI-824. With ability to connect a PMC module on the CPCI-824, up to two devices
are supported.  Otherwise, with a few exceptions, the standard signals defined for 64-bit CPCI
connectors are used for the PMC Modules. The exceptions are noted in Section A.3. The timing for
devices on PMC Modules is the same as the timing for any other PCI device; see the 

PCI Local Bus

Specification

 revision 2.2 for details.  The CPCI-824 PMC module location is defined as +3.3V

signalling.  Note that only +3.3V or universal signalling PMC modules may be used on the CPCI-824.

A number of PMC Modules are available from Cyclone Microsystems. This section is intended for
users interested in developing their own modules.

A.2

PHYSICAL ATTRIBUTES

Please refer to IEEE P1386/Draft 2.0 for the physical dimensions of PMC modules.

A.3

PMC MODULE SIGNAL DEFINITIONS

PMC Modules use the signals defined in the IEEE STD P1386.1. The following four signals are added
to this definition to handle the expansion from one to two devices per PMC module:

GNT1#

REQ1#

CLK1

IDSEL1

Please note that the added signals used the PMC-RSVD signals as defined in IEEE STD P1386.1. The
PCI-RSVD remain untouched.

Also, note that GNT1# follows the description for GNT#, REQ1# follows the description for REQ#,
CLK1 follows the description for CLK, and IDSEL1 follows the description for IDSEL. When the
appropriate signals are connected to PCI devices on a PMC Module, each device has the full
complement of PCI signals defined in the specification.

IDSEL signals are not provided. The designer of a PMC Module should connect the proper AD signal to
a device’s IDSEL pin. AD21:16 may be used depending on the desired number mapping scheme. The
suggested signal connections are shown in tables A-1 and A-2.

Содержание COMPACTPCI-824 FEP BLADE INTELLIGENT I/O CONTROLLER

Страница 1: ...o any products herein to improve reliability function or design Cyclone Microsystems Inc neither assumes any liability arising out of the application or use of any product or circuit described herein...

Страница 2: ...ETHERNET 2 5 2 7 1 Gigabit Ethernet Port 2 5 2 7 2 Gigabit Ethernet LEDs 2 6 2 7 3 Fast Ethernet Port 2 6 2 7 4 Fast Ethernet LEDs 2 6 2 8 PERIPHERAL BUS 2 7 2 8 1 Flash ROM 2 7 2 8 2 LEDs 2 7 2 8 3...

Страница 3: ...Table 1 2 Environmental Specifications 1 3 Table 2 1 SDRAM Configurations 2 3 Table 2 2 External Interrupts 2 4 Table 2 3 Console Serial Port Connector 2 5 Table 2 4 Gigabit Port Connector 2 5 Table...

Страница 4: ...Table 1 2 Environmental Specifications 1 3 Table 2 1 SDRAM Configurations 2 3 Table 2 2 External Interrupts 2 4 Table 2 3 Console Serial Port Connector 2 5 Table 2 4 Gigabit Port Connector 2 5 Table...

Страница 5: ...the features on the Processor local bus operating at 128 bit and a frequency of 166 MHz The 440GX Peripheral Bus EPC has three devices 8 Mbytes of Flash ROM software LEDs and external revision control...

Страница 6: ...vers Two 10 100 Base TX Ethernet ports Each supports up to 100 Mbps and also uses a RJ45 style modular phone jack In this case the MAC contained within the 440GX interfaces with a Broadcom BCM5248 The...

Страница 7: ...r 3 3V or 5V V I O Table 1 1 CPCI 824 Power Requirements 1 4 ENVIRONMENTAL A small amount of airflow will be required such as is found in a typical Eurocard enclosure Table 1 2 Environmental Specifica...

Страница 8: ...GENERAL INTRODUCTION 1 4 CPCI 824 User s Manual Revision 1 0 January 2006 Figure 1 2 CPCI 824 Physical Configuration...

Страница 9: ...ductor Drive P O Box 58090 Santa Clara CA 95052 8090 800 272 9959 http www national com CompactPCI Specification PICMG 2 0R 3 0 PCI Industrial Computers Manufacturing Group 401 Edgewater Place Suite 5...

Страница 10: ...ze also acts as example code to aid developers in creatnig their own applications Breeze is present on all CPCI 824 systems and its debugging facilities are available during the development cycle Bree...

Страница 11: ...troller Interrupt Controller with 18 external interrupt inputs Four Direct Memory Access DMA Controllers Two 10 100 1Gb Ethernet ports with TCP IP acceleration hardware TAH Two 10 100Mb Ethernet ports...

Страница 12: ...a transfer rate of 333 MHz The CPCI 824 is shipped with unbuffered ECC DDR SDRAM installed in the SoDIMM socket The memory may be expanded by inserting up to a 1 GByte module into the 200 pin SoDIMM s...

Страница 13: ...ircuit board that corresponds to a tab in the socket With the correct orientation established hold the module at an angle to the surface of the CPCI 824 and insert the module into the card edge recept...

Страница 14: ...failure or by an attempt to access an invalid address 2 5 1 External Interrupts On the CPCI 824 the external interrupts are connected to the PPC440GX as shown in Table 2 2 The local PCI interrupts ar...

Страница 15: ...of the BCM5248 ports are used in an SMII configuration 2 7 1 Gigabit Ethernet Port The copper line interface of each Gigabit Ethernet port is a shielded RJ45 modular phone type connector The connecto...

Страница 16: ...ggregated input and output ports exit the panel of the CPCI 824 The pin assignment of Port 0 J8 and port 1 J5 is shown on Table 2 5 Table 2 5 10 100 Fast Port Connector 2 7 4 Fast Ethernet Port LEDs B...

Страница 17: ...the processor can begin execution at the reset the processor can begin execution at the reset vector address FFFF FFFCh The size and start location of each of these regions is defined by Breeze softw...

Страница 18: ...e software The definition for GA 4 0 is shown in Figure 2 3 Figure 2 3 Geographic Addressing Register E800 0001h LED TESTS ACT TLBs set External bus controller set ST0 PCB arbitration priorities set S...

Страница 19: ...FAN MONITORING Two circuits are provided for monitoring of the two fan frequency inputs As in the case of the power supply monitoring signals additional inputs to J2 have been defined for the two fan...

Страница 20: ...point Consult the LM75 data sheet for more details on programming the temperature sensors 2 10 3 Serial EEPROM The first time a CPCI 820 is powered up initial conditions are read from a serial EEPROM...

Страница 21: ...1 0 January 2006 Table 2 8 JTAG Emulator Pin Assignment Signal Pin Pin Signal TDO 1 2 No Connect TDI 3 4 TRST NO Connect 5 6 VREF TCK 7 8 No Connect TMS 9 10 No Connect SYS_HALT 11 12 No Connect No C...

Страница 22: ...Modules are available from Cyclone Microsystems This section is intended for users interested in developing their own modules A 2 PHYSICAL ATTRIBUTES Please refer to IEEE P1386 Draft 2 0 for the physi...

Страница 23: ...cles i e AMP P N 120521 2 are located on the host platform and attach to the plugs i e AMP P N 120527 2 This connector combination allows for a 10 mm board to board spacing See IEEE P1386 Draft 2 0 fo...

Страница 24: ...ND 12 PCI RSVD 13 CLK 14 GND 15 GND 16 GNT 17 REQ 18 5V 19 V I O 20 AD31 21 AD28 22 AD27 23 AD25 24 GND 25 GND 26 C BE3 27 AD22 28 AD21 29 AD19 30 5V 31 V I O 32 AD17 33 FRAME 34 GND 35 GND 36 IRDY 37...

Страница 25: ...BUSMODE3 15 3 3V 16 BUSMODE4 17 PCI RSVD 18 GND 19 AD30 20 AD29 21 GND 22 AD26 23 AD24 24 3 3V 25 IDSEL 26 AD23 27 3 3V 28 AD20 29 AD18 30 GND 31 AD16 32 C BE2 33 GND 34 PMC IDSEL1 35 TRDY 36 3 3V 37...

Страница 26: ...AD62 13 AD61 14 GND 15 GND 16 AD60 17 AD59 18 AD58 19 AD57 20 GND 21 V I O 22 AD56 23 AD55 24 AD54 25 AD55 26 GND 27 GND 28 AD52 29 AD51 30 AD50 31 AD49 32 GND 33 GND 34 AD48 35 AD47 36 AD46 37 AD45...

Страница 27: ...J2 DEFINITION B 1 INTRODUCTION The CPCI 824 utilizes some of the reserved pins in J2 for Fan and Power Supply status information Differences from the CPCI specification are shown in table B 1 Table B...

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