Custom Audio Electronics MT002, Руководство пользователя

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2. PRINT HEAD
MT002
2-4
CLOCK (CLK)
LATCH (LAT)
STROBE (STB)
Tw CLK
DATA OUT (DO)
High : HOLD
Low : THROUGH
td DO
t hold DI
DATA IN (DI)
High : BLACK
Low : WHITE
t setup DI
t hold LAT
High : BLACK
Low : WHITE
t setup LAT
tw LAT t setup STB
DRIVER OUT
tdo
tdo
(Tab.2.4)
2.6 SWITCHING CHARACTERISTICS OF CIRCUIT
The switching characteristic summarized in the following table :
Item SYMBOL MIN. TYP. MAX. UNIT CONDITIONS
- 5 8 V
DD
= 5.0V
Clock frequency fCLK
- 3 5
MHz
V
DD
= 3.3V
Clock width tw CLK 95 (155) - - ns
Data set-up time t setup DI 100 (140) - - ns
V
DD
= 5.0V, f
CLK
= 5MHz
V
DD
= 3.3V, f
CLK
= 3MHz
Data hold time t hold DI 85 - - ns
- 50 -
V
DD
= 5.0V
Data out delay time td DO
- 90 -
ns
V
DD
= 3.3V
Latch width tw LAT 150 - - ns
Latch set-up time t setup LAT 200 - - ns
Latch Hold time t hold LAT 80 - - ns
STB set-up time t setup STB 300 - - ns
Driver out delay time tdo - - 10 (30)
μ
s V
DD
= 5.0V (V
DD
= 3.3V)
Notes : CLK should be used at duty 50% (
±
5%), if operated more than fCLK = 5MHz (or fCLK =
3MHz when VDD = 3.3 V). Also, CLK should be within one cycle , being subject to the ratio
between DATA SET-UP TIME and DATA HOLD TIME is 1:1.
2.7 TIMING CHART
Notes :
Symbol “ “ :
means a negative logic signal.
(Fig.2.3)