Curtiss-Wright SCRAMNet+ SC150 VME6U, Справочник по аппаратуре

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OPERATION
Copyright 2007 5-17 VME6U HARDWARE REFERENCE
5.10.2 Rollover/Reset
A rollover/reset can generate an interrupt by setting Interrupt On General Purpose
Counter/Timer Overflow Mask CSR9[12]. When this bit is set, an interrupt is generated
to the host system whenever the counter register (CSR 13) rolls over or overflows.
Interrupt On Errors mode CSR0[7] must be enabled in order for this to work properly.
The counter/timer will roll over when it reaches 65,535 + 1.
Only one mode may be selected at a time since they use the same counter/timer register
(CSR13) for output.
5.10.3 Presetting Values
The counter/timer register counts upward and may be preset with a value to arrive at the
desired interrupt interval.
EXAMPLE
: To set an interrupt to occur every 100 ms, the counter register is preloaded
with ‘8717’, so that when the counter reaches 65,536, only 100 ms would have passed
instead of 111.8 ms.
The value of ‘8717’ was determined by dividing the desired interrupt time of 100 ms
(100,000
μ
s) by the increment frequency of 1.760
μ
s, which results in 56,818. This is the
number that would be in the counter register after 100 ms. To obtain a starting value of
‘8717’, subtract 56,818 from 65535. The counter/timer will not roll over until it reaches
65,535 + 1.
See Appendix B, pages B-6, B-12, and B-14 for additional information.
5.11 Modes of Operation
5.11.1 Data Filter
Many implementations of shared-memory tend to rewrite data values to memory that
have not actually changed. In order to reduce network traffic, the SCRAMNet
+
board has
the ability to compare the new value with the old value of data and avoid sending
unchanged data values out on the network. This feature is a type of data filtering and can
be enabled without affecting node latency while improving network throughput. See
Figure 5-4 Data Filter Logic.
CSR0[10] and CSR0[11] control the operation of data filtering as shown in Table 5-6
(see Appendix B for details of CSR operation):
•
CSR0[10] enables the data filtering during transmission to the SCRAMNet
+
memory and only for the address space above the first 4 K bytes.
•
CSR0[11] enables the address space of the first 4 K bytes to be data-filtered in
conjunction with CSR0[10].
Table 5-6 Data Filter Options
Bit 11 Bit 10* Result
0 1 Only the address space above 4 K bytes of shared
memory is data-filtered
1 1 All shared memory is data-filtered
* Bit 10 must be ON for any data filtering to take place on that node.