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GTS/DEC/006

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4 Apr. 2019 | DST/Y/040

CURTISSWRIGHTDS.COM 

Gain control bandwidth 

This setting controls how quickly the automatic gain control responds to a change in amplitude; a higher setting (up to 100%)
results in a slower filter response while a smaller setting (say 20%) results in a faster response. 

Offset control bandwidth 

This setting controls how quickly the automatic offset control responds to a change in offset; a higher setting (up to 100%)
results in a slower filter response while a smaller setting (say 20%) results in a faster response.

Loop bandwidth filter

It is desirable to restrict loop bandwidth at higher bit rates. This is to prevent the PLL frequency from moving too far away from
the PCM clock frequency and thereby introducing jitter. 

Choosing fill words

Care must be taken when choosing fill words. For example, 0xAAAA (101010…..) or 0x5555 (010101…..) can result in loss of
sync because 0xAAAA at 20Mb/s looks like 0xAAAA at 10Mb/s when using NRZ-M or NRZ-S. A fill word of, for example,
0x7E7E results in no loss of sync. By the same token, a fill word of 0xCCCC (11001100….) results in the same problem when
using 20mb/s NRZ-L. Therefore, try to avoid repetitions of these types when choosing fill words. 

Loopback tester

The GTS/DEC/006 features a loopback tester, which transmits a PCM frame to allow system checks. The loopback tester
transmits frames as configured in the XidML setup. The loopback tester allows for dynamic and fixed data to be transmitted. The
first eight parameters transmitted are dynamic counters that rollover to zero. The rest of the parameters are a fixed word (which
is 0x1234). At present, the loopback tester only generates the minor frame layout as given in the configuration.

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The GTS/DEC/006 driver software is a minor frame decoder. Client software can use the SDK functions to decommutate 
major frames by adding minor frame tracking logic.

Status LEDs

The GTS/DEC/006 uses LEDs as shown in the following figure to indicate the current status of the card. 

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The state of LEDs is undefined between power-on and the first driver access to the PCI card. Once the card is config-
ured, behavior is as shown in the following table until the PC is powered off.

Figure 2: PCI card LEDs

TABLE 11

Status LED description

LED

NAME

DESCRIPTION

1

IRIG-B

Lights when the IRIG time signal is successfully received.

2

BS(0)

Lights solid green when the bit synchronizer is in lock with an incoming data stream on channel 0.

3

DECOM(0)

Lights solid green when the decommutator is in a lock state; when not lit the decommutator is in a loss, 
verify or check state.

4

BS(2)

Lights solid green when the bit synchronizer is in lock with an incoming data stream on channel 2.

5

BS(1)

Lights solid green when the bit synchronizer is in lock with an incoming data stream on channel 1.

1

2

3

4

5

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Содержание GTS/DEC/006

Страница 1: ...emetry data links Overview The GTS DEC 006 reconstructs a serial PCM data stream from a source that has been corrupted by noise phase jitter amplitude modulation or base line variations The all digital design utilizes three independent programmable matched filters and Phase Locked Loops PLL to track deviations in the bit rate of the received signals The output from the bit synchronizers is fed int...

Страница 2: ... W Environmental ratings operating temperature 10 50 C storage temperature 25 70 C TABLE 2 BTTL inputs PARAMETER MIN TYP MAX UNITS CONDITION DETAILS Inputs 3 Signaling rate PCM_IN_DCLK 0 20 Mbps PCM_IN_DATA 0 20 Mbps NRZ L M S RNRZ L 11 13 15 17 23 PCM_IN_DATA 0 10 Mbps BIØ L IRIG B_IN 1 Mbps Digital IRIG B 000 001 002 003 time formats Input voltage operating range 0 5 5 V logic 0 0 8 V logic 1 2 ...

Страница 3: ...TER MIN TYP MAX UNITS CONDITION DETAILS Outputs 5 Signaling rate BITSYNC_OUT_DATA 0 20 Mbps NRZ L M S RNRZ L 11 13 15 17 23 BITSYNC_OUT_DATA 0 10 Mbps BIØ L BITSYNC_OUT_DCLK 0 20 MHz LOOPBACK_OUT_DATA 20 Mbps NRZ L M S RNRZ L 11 13 15 17 23 LOOPBACK_OUT_DATA 10 Mbps BIØ L LOOPBACK_OUT_DCLK 20 MHz SMART_OUT For details see SMART_OUT output on page 5 Output voltage absolute operating range 7 12 V Ab...

Страница 4: ...BIØ L 0 064 10 000 kbps Maximum DC offset single ended 5 5 V differential ended 10 10 V TABLE 6 Bit synchronizer performance PARAMETER MIN TYP MAX UNITS CONDITION DETAILS Loop bandwidth 0 01 2 0 Offset bandwidth 100 Gain bandwidth 100 Acquisition range 0 04 5 Tracking range 0 1 20 Bit Error Rate 0 2 1 dB Deviation from theory Sync maintenance Retains sync with NRZ codes at EbNo 3dB with 248 transi...

Страница 5: ...ting XidML metadata files and programming the card It also offers real time access to decommutated data with time tags and status registers Bit synchronizer performance tuning If offset modulation is affecting performance adjust the offset bandwidth from 100 downwards to compensate Likewise if amplitude modulation is affecting performance decrease the gain bandwidth TABLE 8 Bit synchronizer settin...

Страница 6: ...llow system checks The loopback tester transmits frames as configured in the XidML setup The loopback tester allows for dynamic and fixed data to be transmitted The first eight parameters transmitted are dynamic counters that rollover to zero The rest of the parameters are a fixed word which is 0x1234 At present the loopback tester only generates the minor frame layout as given in the configuratio...

Страница 7: ...t the aligner is not able to find the alignment point in the data PINS DESCRIPTION 1 Connects a 50Ω load between the input and GND for single ended input default 2 Connects a 75Ω load between the input and GND for single ended input 3 Connects the input to GND for single ended input default 4 Connects a 120Ω load between the input and the input for differential ended signals TABLE 12 Programmable ...

Страница 8: ...idth can be set Maximum Stuck Bit Length This setting is used to determine when a channel is considered stuck at 1 or 0 due to bad signal conditions That is the design allows a sequence for up to 48 default bits to be 1 or 0 without change before it declares the channel to be stuck If you are using line codes such as RNRZ L or Bi Phase L the setting never comes into effect since you always have tr...

Страница 9: ...nect 20 GND GTS 500 internal ground 21 DNC Do not connect 22 GND GTS 500 internal ground 23 BITSYNC_OUT_DCLK 0 RS 422 outputs Differential ended bit synchronizer clock output 24 BITSYNC_OUT_DCLK 0 RS 422 outputs Differential ended bit synchronizer clock output 25 BITSYNC_OUT_DATA 0 RS 422 outputs Differential ended bit synchronizer data output 26 BITSYNC_OUT_DATA 0 RS 422 outputs Differential ende...

Страница 10: ...ing software Related products Related documentation PART NUMBER DESCRIPTION GTS DEC 006 C Smart Source Selector and PCM decommutator PCI board 20Mbps 3ch REVISION DIFFERENCES STATUS GTS DEC 006 C First release Recommended for new programs SOFTWARE DETAILS GTS SDK 3 Software development kit for GTS boards XidML 3 0 DAS Studio 3 User interface for setup and management of data acquisition network swi...

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