Curtiss-Wright FHK4-FM4MWB04-00, Справочник по аппаратуре

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REHOSTABLE CMC FPDP INTERFACE
Copyright 2012 11-16 FibreXtreme HW Reference for FPDP Cards
Signal Name Signal
Direction
Signal Description
TSTROBE Output FPDP Transmitter Clock Output. This is a clock-divided version of the
reference clock (53.125 MHz or 125 MHz). This clock’s frequency is determined
by CLK_CFG[1:0]. All signals sent to the FPDP interface are synchronized to
this clock.
/TSUSPEND Input Transmit Suspend. This signal asserts flow control to the FPDP interface. It
should be set to ‘0’ when the FPDP receiver has less than two words of space
left in its receive FIFO. Otherwise, set to ‘1’. Data will not start transmitting if
/TSUSPEND is set to ‘0’.
/TSYNC Output Transmit Synchronization. This signal is a ‘0’ when a /TSYNC is clocked out
of the Receive FIFO. Otherwise, it is a ‘1’. The transmitter at the remote end
determines if /TSYNC with /TDVALID or /TSYNC without /TDVALID is sent.
11.5 Programmed Inputs/Outputs (PIOs)
The PIO1_IN, PIO2_IN and /RESET inputs to the rehostable CMC FPDP card are shared
between the transmit (P4) and receive (P6) interfaces. These signals should always be
driven from the same source to avoid logic contention and possible damage to the
hardware. The PIO1_OUT and PIO2_OUT signals are also shared between the P4 and P6
connectors. Figure 11-6 shows the connection of these signals on the CMC card.
PIO1_IN
PIO2_IN
PIO1_OUT
PIO2_OUT
/RESET
P6 CONNECTOR
P3 CONNECTOR
P4 CONNECTOR
Figure 11-6 PIO Line Interconnectivity
The state of the PIO lines is transmitted across the link interface, embedded in the Start
Of Frame (SOF) ordered set. Refer to Appendix D, SL100/SL240 Protocol, for more
information.