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Appendix A. DIP Switch Settings

TRM-01 APR 2000

DIPSW3

DIP SW3

STATE

FUNCTION

COMMENT

-1

OFF

Time slot 9 disable

Time slot 9 enable

-2

OFF

Time slot 10 disable

Time slot 10 enable

-3

OFF

Time slot 11 disable

Time slot 11 enable

-4

OFF

Time slot 12 disable

Time slot 12 enable

-5

OFF

Time slot 13 disable

Time slot 13 enable

-6

OFF

Time slot 14 disable

Time slot 14 enable

-7

OFF

Time slot 15 disable

Time slot 15 enable

-8

OFF

Time slot 16 disable

Time slot 16 enable

Table A-3 : DIPSW3 TIME SLOT 9 TO 16 SETTING

DIPSW4

DIP SW4

STATE

FUNCTION

COMMENT

-1

OFF

Time slot 17 disable

Time slot 17 enable

Note 1

-2

OFF

Time slot 18 disable

Time slot 18 enable

-3

OFF

Time slot 19 disable

Time slot 19 enable

-4

OFF

Time slot 20 disable

Time slot 20 enable

-5

OFF

Time slot 21 disable

Time slot 21 enable

-6

OFF

Time slot 22 disable

Time slot 22 enable

-7

OFF

Time slot 23 disable

Time slot 23 enable

-8

OFF

Time slot 24 disable

Time slot 24 enable

Table A-4 DIPSW4 TIME SLOT 17 TO 24 SETTING

Содержание TRM01

Страница 1: ......

Страница 2: ......

Страница 3: ...ties 6 Chapter 2 Installation 9 2 1 General 9 2 2 Site Preparation 9 2 3 Mechanical Assembly 9 2 4 Electrical Installation 10 2 5 Power Supply Modules 12 Chapter 3 Data Modules 13 3 1 Data Modules Ove...

Страница 4: ...ck 23 4 4 Data Port local analog loop back 24 4 5 T1 Link remote loop back 24 4 6 BERT local loop back 25 4 7 BERT remote loop back for system test 25 Chapter 5 Troubleshooting 27 5 1 General 27 5 2 C...

Страница 5: ...n the rear panel BNC and Terminal Blocks are used for T1 Line interface connections while optional cable adapters are used to convert the HDB26 DCE ports to V 35 RS 530 RS 449 or X 21 When an FT1 ET10...

Страница 6: ...r LED flashes for each bit error detected Multiple clock source selection provides maximum flexibility in connecting both the T1 and user data interface The T1 link may be clocked from the recovered r...

Страница 7: ...and Tx clock recovered from T1 Zero amplitude 0 1V Transmit Frequency Tracking Mode 1 DCE2 Rx and Tx clock internal oscillator Internal timing 30ppm Mode 2 DTT1 Sync to Rx clock transparent Loopback t...

Страница 8: ...known as the superframe SF format to frame data at the physical layer The D4 format consists of 12 consecutive frames each separated by framing bits Framing is necessary in order for equipment receiv...

Страница 9: ...ine code in which bipolar violations are deliberately inserted if user data contains a string of 8 or more consecutive zeros Note 1 B8ZS is used to ensure a sufficient number of transitions to maintai...

Страница 10: ...lot assignments data rates from 64Kbps up to 1536Kbps may be utilized in frame mode The FT1 Cards in the TRM 01 could all be set to internal oscillator timing or they could receive timing from the DTE...

Страница 11: ...1 frame the TRM 01 could be used as a 13 data channel multiplexer It should also be noted however that removal or failure of any one card in this configuration would negatively effect all other card d...

Страница 12: ...Chapter 1 Introduction 8 TRM 01 APR 2000 This page left blank intentionally...

Страница 13: ...t should be capable of furnishing 90 to 250 VAC Allow at least 10cm 4 inch clearance at the rear of the TRM 01 for signal lines and interface cables 2 3 Mechanical Assembly The TRM 01 is designed for...

Страница 14: ...ective earth lead of the power cable in AC installations or via the ground connection for DC installations The line fuses for the TRM 01 are located on the Power Module units themselves Access to the...

Страница 15: ...e interface connector groups are provided for each slot The T1 signals may use either the Rx Tx BNC pair for unbalanced transmissions or the 5pin Molex connectors with terminal block adapters for bala...

Страница 16: ...ated on the Power Module card s The AC power is rectified and filtered before being passed to the regulator module The regulator module is factory adjusted to provide 48VDC to the back plane with comp...

Страница 17: ...der power will not effect the operation of other FT1 cards The one exception to this would be a case where the improper fuse rated too high were placed on a defective FT1 card causing the main AC or D...

Страница 18: ...TRM 01 APR 2000 Figure 3 2 FT1 Card Detail Push button switches for Test Loop Back Power Status and Alarm LEDs 9 Interface Connector DC DC Converter Power Protection Fuse Configuration DIP Switches H...

Страница 19: ...DCD yellow LEDs indicate status of the data communication port The red TxCLK signal loss sync loss and alarm LEDs all indicate error conditions on the T1 line or link connection When loop back testin...

Страница 20: ...rier signal is active between the DSU and the connected DTE equipment TxCLK Loss This red LED will light in the event of CSU clock signal loss Sig Loss This red LED will light in the event of CSU sign...

Страница 21: ...r cable follows the pin out standards shown below exactly Abbreviation HDB26 PIN MB34 PIN V 35 Circuit FG 1 A Frame SG 7 B Signal Ground TD A TD B 2 11 P S TD A TD B RD A RD B 3 21 R T RD A RD B RTS A...

Страница 22: ...hown below exactly Abbreviation HDB26 PIN DB25 PIN RS 530 Circuit FG 1 1 Frame SG 7 7 AB TD A TD B 2 11 2 14 BA A BA B RD A RD B 3 21 3 16 BB A BB B RTS A RTS B 4 13 4 19 CA A CA B CTS A CTS B 5 14 5...

Страница 23: ...low exactly Abbreviation HDB26 PIN DB37 PIN RS 449 Circuit FG 1 1 Frame SG 7 19 20 37 SG RC SC TD A TD B 2 11 4 22 SD A SD B RD A RD B 3 21 6 24 RD A RD B RTS A RTS B 4 13 7 25 RS A RS B CTS A CTS B 5...

Страница 24: ...r cable follows the pin out standards shown below exactly Abbreviation HDB26 PIN DB15 PIN X 21 Circuit FG 1 1 Shield SG 7 8 Ground TD A TD B 2 11 2 9 Transmit A Transmit B RD A RD B 3 21 4 11 Receive...

Страница 25: ...daughter board Refer to Figure 3 4 Pull the board straight out and avoid bending the pins After setting press the daughter board back onto the FT1 Card closely observing the 20 and 26 pin connectors...

Страница 26: ...RIDGE LAN Table 10 000 MAC address with 5 minute automatic aging Filtering and Forwarding 15 000 frames sec Buffer 256 frames Delay 1 frame LAN Standard Conforms to IEEE 802 3 10Base T Ethernet Data R...

Страница 27: ...CK PARAMETER menu under ASCII terminal mode or via SNMP The latter two methods both require the optional SNMP Card installed and will not be discussed any further here The available test functions via...

Страница 28: ...er doing this test when the data port is ET10 Ethernet bridge or collisions may result Loc ana loopbk depressed Figure 4 2 Data port local analog loop back 4 5 T1 link remote loop back The local FT1 C...

Страница 29: ...smitted patterns and detects errors as shown in Figure 4 4 Err LED should be off during successful loop back Pattern and Loc ana loopbk depressed Figure 4 4 BERT for local test 4 7 BERT remote loop ba...

Страница 30: ...Chapter 4 Loop Back Testing 26 TRM 01 APR 2000 This page left blank intentionally...

Страница 31: ...l comply with ITU G 703 recommendations it is very important to understand the differences in terminology between different equipment manufactures A thorough understanding of the settings and configur...

Страница 32: ...requested only eight 8 timeslots are required to carry the data payload Carefully check the settings at the central site and confirm that the same eight timeslots are active on each end of the link C...

Страница 33: ...T1 BERT unframed 100 ohm termination B8ZS line code external Tx and Rx clock QRSS pattern and run forever Run the BERT Confirm 1 536Mbps rate and no receive errors If testing a remote link inject a f...

Страница 34: ...th the Pattern and Loc ana loopback switches The pattern generator is internally connected to the DSU side while the loop back is placed on the CSU in analog mode Refer to Figure 4 4 on page 25 The re...

Страница 35: ...h Pattern switches on each card Now each pattern generator is sending to the other card while each pattern tester is receiving the 511 bit pattern from the other card The same successful indicators as...

Страница 36: ...Chapter 5 Troubleshooting 32 TRM 01 APR 2000 This page left blank intentionally...

Страница 37: ...ng See Table A 7 Table A 1 DIP SWITCH FUNCTION DESCRIPTIONS DIPSW2 DIP SW2 STATE FUNCTION COMMENT 1 OFF Time slot 1 disable Note 1 ON Time slot 1 enable Note 2 2 OFF Time slot 2 disable ON Time slot 2...

Страница 38: ...ble ON Time slot 15 enable 8 OFF Time slot 16 disable ON Time slot 16 enable Table A 3 DIPSW3 TIME SLOT 9 TO 16 SETTING DIPSW4 DIP SW4 STATE FUNCTION COMMENT 1 OFF Time slot 17 disable ON Time slot 17...

Страница 39: ...ecovery 1 ON OFF OFF Clock mode 1 DCE2 Internal Osc 1 OFF ON OFF Clock mode 2 DTE1 Transparent 1 ON ON OFF Clock mode 3 DTE2 Data Port 1 OFF OFF ON Clock mode 4 DTE3 Data Port 1 ON OFF ON Reserve OFF...

Страница 40: ...panel pushbuttons This will prevent un authorized or accidental link breakage In order for the front panel switches to function this setting must be ON By default it is ON from the factory CLOCK MODE...

Страница 41: ...Appendix A DIP Switch Settings 37 TRM 01 APR 2000 This page left blank intentionally...

Страница 42: ...notes 38...

Страница 43: ...notes 39...

Страница 44: ...Timeslot 17 2 Timeslot 18 3 Timeslot 19 4 Timeslot 20 5 Timeslot 21 6 Timeslot 22 7 Timeslot 23 SW4 8 Timeslot 24 1 Line Build Out Setting 2 Line Build Out Setting 3 Line Build Out Setting 4 Reserved...

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Страница 48: ...logies Co Ltd Far Eastern Edison Science and Technologies Center Nei Hu HI TEC Park 6F 3 Lane 360 Nei Hu Road Section 1 Nei Hu Taipei Taiwan Phone 886 2 2659 1021 Rep Fax 886 2 2799 1355 E mail ctcu m...

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