Crown XLS 1000 Series, Руководство по обслуживанию

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The DSP runs at 48KHz sampling rate and also requires that the external codec
also samples at 48KHz. The DSP utilizes I2S digital audio to get audio to/from
the external codec (DSP_SDIN, DSP_SDOUT). The timing diagram below
shows the relationship between serial clock (SCLK), channel clock (LRCK), and
digital audio (SDIN, SDOUT).
CLIP Inputs:
The Ruby IC (U1) on the MAIN PWA supplies individual channel clip
indications via J700. In order to get these clip indications directly into the TI DSP
(U703) as an input for the clip compressor, a 2
nd
I2S input is used. The channel
clip indications (CLIP1 & CLIP2) are gated into their own I2S channel using the
LRCK signal and U708. CLIP1 events are gated onto the ‘L’ I2S channel and the
CLIP2 events are gated onto the ‘R’ I2S channel. This provides 48KHz sampling
of the Ruby clip events into the DSP for the clip compressor.
Serial Communications:
The TAS3202 has two I2C channels: I2C1 and I2C2 for external communications
and booting. The DSP initially tries to use I2C2 to access an external EEPROM
to boot itself. In this design, an external EEPROM is not used and the DSP is
booted from the microprocessor (U706) via I2C1. The DSP acts as a slave with
the processor being the master. Control for filter selection, frequency setting,
input level monitoring, clip events, and other control and monitoring functions are
handled thru this serial communications port.
NOTE: Don’t confuse I2 C with I2 S
. Both are used in this device. I2C is a 2-
wire serial communications protocol that allows an external processor to boot,
monitor, and control the TAS3202. I2S is a 3-wire serial digital audio
protocol that supports 2 channels of real-time audio and allows digital audio to
move in and out of the TAS3202.