Micro-Tech 600 Amplifier Service Manual
11
respect to each other. This allows the power supply to
dVcc and -Vcc from the same bridge rectifier
and filter as a total difference in potential, regardless
of their voltages with respect to ground. The LS uses
inverted feedback from the HS output to control the
ground reference for the rails (±Vcc). Both LS quad-
rants are arranged in a three-deep Darlington and are
biased AB+B in the same manner as the HS.
When the amplifier output swings positive, the audio is
fed to an op-amp stage where it is inverted. This
inverted signal is delivered directly to the bases of the
positive (NPN) and negative (PNP) LS predrivers. The
negative drive forces the LS PNP devices on (NPN
off). As the PNP devices conduct, Vce of the PNP
Darlington drops. With LS device emitters tied to
ground, -Vcc is pulled toward ground reference.
Since the power supply is not ground referenced (and
the total voltage from +Vcc to -Vcc is constant) +Vcc
is forced higher above ground potential. This contin-
ues until, at the positive amplifier output peak, -Vcc =
0V and +Vcc equals the total power supply potential
with a positive polarity. If, for example, the power
supply produced a total of 70V from rail to rail (±35VDC
measured from ground with no signal), the amplifier
output would reach a positive peak of +70V.
Conversely, during a negative swing of the HS output
where HS PNP devices conduct, the op-amp would
output a positive voltage forcing LS NPN devices to
conduct. This would result in +Vcc swinging toward
ground potential and -Vcc further from ground poten-
tial. At the negative amplifier output peak, +Vcc = 0V
and -Vcc equals the total power supply potential with
a negative polarity. Using the same example as above,
a 70V supply would allow a negative output peak of -
70V. In summary, a power supply which produces a
total of 70VDC rail to rail (or ±35VDC statically) is
capable of producing 140V peak-to-peak at the ampli-
fier output when the grounded bridge topology is
used. The voltage used in this example are relatively
close to the voltages of the PB-1/460CSL.
The total effect is to deliver a peak to peak voltage to
the speaker load which is twice the voltage produced
by the power supply. Benefits include full utilization of
the power supply (it conducts current during both
halves of the output signal; conventional designs
require two power supplies per channel, one positive
and one negative), and never exposing any output
device to more than half of the peak to peak output
voltage (which does occur in conventional designs).
Theory
Low side bias is established by a diode string which
also shunts built up charges on the output devices.
Bias is adjustable via potentiometer. Flyback diodes
perform the same function as the HS flybacks. The
output of the LS is tied directly to chassis ground via
ground strap.
OUTPUT DEVICE EMULATION PROTECTION
(ODEP)
To further protect the output stages, a specially devel-
oped ODEP circuit is used. It produces a complex
analog output signal. This signal is proportional to the
always changing safe-operating-area margin of the
output transistors. The ODEP signal controls the Volt-
age Translator stage by removing drive that may
exceed the safe-operating-area of the output stage.
ODEP senses output current by measuring the volt-
age dropped across LS emitter resistors. LS NPN
current (negative amplifier output) and +Vcc are
sensed, then multiplied to obtain a signal proportional
to output power. Positive and negative ODEP voltages
are adjustable via two potentiometers. Across ±ODEP
are a PTC and a thermal sense (current source). The
PTC is essentially a cutoff switch that causes hard
ODEP limiting if heatsink temperature exceeds a safe
maximum, regardless of signal level. The thermal
sense causes the differential bODEP and –
ODEP to decrease as heatsink temperature increases.
An increase in positive output signal output into a load
will result in –ODEP voltage dropping; an increase in
negative output voltage and current will cause +ODEP
voltage to drop. A complex RC network between the
±ODEP circuitry is used to simulate the thermal barri-
ers between the interior of the output device die
(immeasurable by normal means) and the time delay
from heat generation at the die until heat dissipates to
the thermal sensor. The combined effects of thermal
history and instantaneous dynamic power level result
in an accurate simulation of the actual thermal condi-
tion of the output transistors.
