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6. Appendix
62
PT-S959W10 User’s manual
POST Codes
Table 6.4. POST Codes < 1 / 3 >
POST (hex) Description
< Security (SEC) phase >
1h Power on. Reset type detection (software / hardware)
2h AP initialization before microcode loading
3h North Bridge initialization before microcode loading
4h South Bridge initialization before microcode loading
5h OEM initialization before microcode loading
6h Microcode loading
7h AP initialization after microcode loading
8h North Bridge initialization after microcode loading
9h South Bridge initialization after microcode loading
Ah OEM initialization after microcode loading
Bh Cache initialization
< Pre-EFI Initialization (PEI) phase >
10h PEI Core is started
11h Pre-memory CPU initialization is started
12h – 14h Pre-memory CPU initialization (CPU module specific)
15h Pre-memory North Bridge initialization is started
16h – 18h Pre-Memory North Bridge initialization (North Bridge module specific)
19h Pre-memory South Bridge initialization is started
1Ah – 1Ch Pre-memory South Bridge initialization (South Bridge module specific)
1Dh – 2Ah OEM pre-memory initialization codes
2Bh Memory initialization. Serial Presence Detect (SPD) data reading
2Ch Memory initialization. Memory presence detection
2Dh Memory initialization. Programming memory timing information
2Eh Memory initialization. Configuring memory
2Fh Memory initialization (other).
30h Reserved for ASL (see ASL Status Codes section below)
31h Memory Installed
32h CPU post-memory initialization is started
33h CPU post-memory initialization. Cache initialization
34h CPU post-memory initialization. Application Processor(s) (AP) initialization
35h CPU post-memory initialization. Boot Strap Processor (BSP) selection
37h CPU post-memory initialization. System Management Mode (SMM) initialization
38h Post-Memory North Bridge initialization is started
39h – 3Ah Post-Memory North Bridge initialization (North Bridge module specific)
3Bh Post-Memory South Bridge initialization is started
3Ch – 3Eh Post-Memory South Bridge initialization (South Bridge module specific)
3Fh – 4Eh OEM post memory initialization codes
4Fh DXE IPL is started
< Driver Execution Environment (DXE) phase >
60h DXE Core is started
61h NVRAM initialization
62h Installation of the South Bridge Runtime Services
63h CPU DXE initialization is started
64h-67h CPU DXE initialization (CPU module specific)
68h PCI host bridge initialization
69h North Bridge DXE initialization is started
6Ah North Bridge DXE SMM initialization is started