Contec DA16-16L, Руководство пользователя

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6. About Hardware
68
DA16-16(LPCI)L, DA16-8(LPCI)L
Timing for Control Signal
Timing for Analog Output Control Signal
Figures 6.3, 6.4, 6.5, and Table 6.3 shows the timing for analog output control signal.
Figure 6.3. Timing for External Sampling Clock (Analog output)
Figure 6.4. Timing for Sampling Start Control Signal
Figure 6.5. Timing for Sampling Stop Control Signal
Table 6.3. Timing List for Control Signal
Parameter Symbol Time Unit
Delay from external sampling clock to actual start t
DEC
100 nsec
Settling time t
WS
10000 nsec
Set up time of sampling start (Rising edge) t
SRS
100 nsec
Hold time of sampling start (Rising edge) t
HRS
100 nsec
Set up time of sampling start (Falling edge) t
SFS
100 nsec
Hold time of sampling start (Falling edge) t
HFS
100 nsec
Set up time of sampling stop (Rising edge) t
SRP
100 nsec
Hold time of sampling stop (Rising edge) t
HRP
100 nsec
Set up time of sampling stop (Falling edge) t
SFP
100 nsec
Hold time of sampling stop (Falling edge) t
HFP
100 nsec
The times listed in Table 6.3 are for standard operating conditions.
External Smapling Clock Input
t
DEC
Conversion start
External Smapling Start Trigger Input
t
HRS
t
SRS
t
HFS
t
SFS
External Smapling Stop Trigger Input
t
HRP
t
SRP
t
HFP
t
SFP
CAUTION