Contec AIO-160802AY-USB, Руководство пользователя

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7. About Hardware
Control Signal Timings for Analog Output
Figures 7.6, 7.7, 7.8, and Table 7.3 show the control signal timings for the analog output function.
t
DEC
External Smapling Clock Input
t
DEH
Conversion start
Figure 7.6. Timing Chart of External Sampling Clock (Analog output)
External Smapling Start Trigger Input
t
HRS
t
SRS
t
HFS
t
SFS
Figure 7.7. Timing Chart of Sampling Start Control Signal
External Smapling Stop Trigger Input
t
HRP
t
SRP
t
HFP
t
SFP
Figure 7.8. Timing Chart of Sampling Stop Control Signal
Table 7.3. Control Signal Timings
Parameter Symbol Time Unit
Delay from external sampling clock to actual start t
DCS
100 nsec
Settling time t
WS
10000 nsec
Set up time of sampling start (Rising edge) t
SRS
100 nsec
Hold time of sampling start (Rising edge) t
HRS
100 nsec
Set up time of sampling start (Falling edge) t
SFS
100 nsec
Hold time of sampling start (Falling edge) t
HFS
100 nsec
Set up time of sampling stop (Rising edge) t
SRP
100 nsec
Hold time of sampling stop (Rising edge) t
HRP
100 nsec
Set up time of sampling stop (Falling edge) t
SFP
100 nsec
Hold time of sampling stop (Falling edge) t
HFP
100 nsec
CAUTION
The times listed in Table 7.3 are for standard operating conditions.
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AIO-160802AY-USB