Conner CFP4207 Series, Руководство по эксплуатации продукта

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Chapter 1 Overview of the Drives
Page 6 Filepro CFP4207 Series
The background processor is a 16-bit Motorola 68HC16. The entire data path
between the serializer-deserializer and the interface chip, including the buffer
(cache) is 16 bits wide to provide high data throughput. The SCSI interface chip
manages a 16-bit to 8-bit conversion prior to transacting data over the SCSI bus
for 8-bit narrow SCSI applications.
The data buffer (cache) utilizes a 256K x 16 Dynamic RAM. Data path integrity
is ensured by using a 4-byte CRC which is appended to the data upon receipt by
the Catalina. This CRC is verified by the buffer manager when the data is taken
out of the buffer to be written to the disk and the CRC is written with the data.
A typical sector data field consists of 512 bytes of data, 4 bytes of CRC and 11
bytes of Error Detection And Correction (EDAC) code. The same CRC checks are
performed during an outbound process and the CRC is stripped from the data
prior to sending it to the Host.
The SCSI interface functions are managed by a 8-bit Motorola 68HC11
microprocessor. Low SCSI transaction overhead is maintained by automating
common SCSI bus phase sequencing using a state machine in the SCSI Interface
Chip.
Read/Write Channel
The Read/Write channel, in addition to the preamplifier discussed earlier,
consists of three integrated circuits:
•
Pulse Detector
•
Data Separator
•
Time base
Firmware
The drive’s firmware can be considered in two parts. The first part principally
resides in the ROM for the 68HC16 background processor. This processor is
responsible for:
•
starting the spindle motor and maintaining precise rotational speed
•
controlling track following and actuator motion during seeking
•
managing background R/W activity
•
power management
•
monitoring the overall health of the drive.
The interface processor's control microcode resides in both ROM and RAM. The
RAM portion of the microcode can be upgraded in the field with using software.
Additional information regarding the RAM code can be found in Chapter 3, page
22. The interface processor firmware functions include:
•
reporting drive status and error conditions to the host
•
manage operating parameters for the drive
•
parsing the Command Descriptor Block and checking for illegal fields
•
converting the LBA to CHS and initiating read and write operations to the
background processor
•
defect management