Comtech EF Data CDM-550T, Руководство пользователя

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CDM-550T Satellite Modem Clocking
Rev. 1.3 10–3
10.2.3 Buffer Enabled, RX<>TX
This is an uncommon case, where the receive and transmit data rates are not
equal. The modem will generate a phase-locked buffer output clock which uses the
transmit clock, regardless of its frequency in relation to the receive data rate.
10.3 X.21 Notes
For X.21 operation, use the RS422 pins, but ignore Receive Clock if the Modem is DTE,
and ignore Transmit clocks if the Modem is DCE.
10.4 Loop Timing With Sync EIA-232
The CDM-550T distinguishes between synchronous and asynchronous EIA-232 by
detecting clock activity on the TX Clock pin of the interface. If no clock is detected, it is
assumed that the mode is asynchronous. Therefore, if loop timing is employed in a
synchronous EIA-232 application, it is essential to provide an external loop between the
ST and TX clock pins. If this is not done, the modem will assume an async mode, which
is not compatible. The loop should be placed between pin 15 and pin 24 on the 25 pin ‘D’
type interface.
THE FOLLOWING TWO PAGES ILLUSTRATE IN BLOCK-DIAGRAM FORM THE
VARIOUS TRANSMIT AND RECEIVE CLOCK MODES.