CommTech FASTCOM ESCC-PCI-335, Справочник по аппаратуре, Страница: 25 / 33

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To use Master clock mode or not to use Master clock mode; that is the question.
The 82532 operating in standard (non-master clock) mode uses the transmit clock source (refer to table 5 page
84 of the data sheet) to run the internal timing of the chip. If your transmit clock source is running very slow or it is
not running continuously (if external clock is supplied), then it is a good idea to switch to master clock mode.
Each command issued to the 82532 (any write to the CMDR register) can take up to 2.5 clocks to complete. If the
clock is very slow or stops from time to time, this can be a significant amount of time and allows for the possibility
of a command being lost (written but not executed, because a previous command is not complete). If your baud
rate is slow (<1MHz) or you are using a gated external clock, you should use master clock mode to allow the PC
interface to the 82532 to continue to execute quickly. If this mode is used, then the OSC input must be less than
10MHz (the speed rating of the internals of the 82532). If you have a 82532 rev 3.x (silicon), then you can cause
the master clock to be OSC/4 by setting CCR4 bit 7 (MCK4), thus allowing the 10MHz restriction to be lifted.
If you are using a clock mode that uses external clocks, you should respect the restriction on the ratio of receive
to transmit clock frequency given in note 2 of table 5 (Freceive/Ftransmit <3 or 1.5).
If you are running in not extended baud rate mode, do not set BGR bits 5-0 to all = 0, or the chip will assume that
all of the BGR bits are 0. This is a glitch in the 82532 rev 3.2 and makes the following values for N identical:
0x000,0x040,0x080,0x0C0
0x100,0x140,0x180,0x1C0
0x200,0x240,0x280,0x2C0
0x300,0x340,0x380,0x3C0
Setting the baud rate generator to any of these values will produce the same affect as setting it to 0x000.
If you use the Enhanced baud rate generator and set m = 0, the clock output will be asymmetric (non 50/50 duty
cycle).
An important fact about the clock generator
There is only one programmable clock generator, and only 1 OSC input to the 82532 chip. The clock generator
can be programmed from either channel (ESCC0 or ESCC1), but it programs the same part. The result is that
while the baud rate generators are unique on a per channel basis, the OSC input is not (i.e., the baud rate
generators are independent, but the clock that feeds them is the same). If you change the clock generator output
you will change the input clock to both channels. The practical thing to note about this is that if you have multiple
baud rates that must be generated on multiple channels, you should select the input clock such that all baud rates
can be derived from one clock value. Changing the clock generator output will affect the baud rates of both
channels (ESCC0, ESCC1)!!!!
If you are using HDLC or Bisync as a data format, there is not a BCR setting (no oversampling). However, if you
select a clock mode that uses the DPLL as a source, it will effectively add a divide by 16 to your function.
Selecting the appropriate clock mode is a matter of identifying what clock signals are available external to the
Fastcom card, and what clock signals are required by the external device. The simplest mode is using external
clocks only (mode 0a); in this mode both the receive and transmit timing are taken from the connector (RT for
receive, ST for transmit). The rest of the modes are a mix of external signals and internally generated
clocks/clock recovery. The DPLL modes only operate up to 2 MHz. If the bitrate is above that, you should use a
non-DPLL mode.
The bitrate functions are similar to the async case:
If you are not using a clock mode that uses the DPLL, the formula is:
bitrate = (input clock / BGR)
If you are using the DPLL, the formula is:
bitrate = (input clock / BGR)/16