MPX-8188
User’s Manual
-6-
4.4 < Power UP Sequencing >
RTL8188EE PCIe Bus Power Sequence
T
on
:
The main power ramp up duration
T
PVCRL
:
Power valid to CLKREQ# output active
T
PVPGL:
Power valid to PERST# input inactive
T
PERST#CLK
:
Reference clock stable before PERST# inactive
The typical timing range
Symbol
Unit
Min
Typical
Max
T
on
ms
--
1.5
5
T
PVCRL
us
--
100
T
PVPGL
ms
1
--
T
PERST#CLK
us
100
--
3.3V
CLKREQ#
PERST#
REFCLK
T
on
T
PVCRL
T
PVPGL
T
PERST#CLK
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