CNET CSH-24X2G, Руководство пользователя

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Misc Configuration
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[1] MIB Counter
[2] Device Feature
[3] Global
[4] Security
[5] Load Factory Default
[6] Overview
[7] Diagnostics
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Function Key
[ ]To select menu item, press item symbol. [0]Return [F]Refresh Screen
4.6.1 MIB Counter
The MIB counters are 32-bit counters. After power on Reset, the counters are all reset to 0. A read
access of the MIB counter will NOT reset the counter to 0.
The time before the next read of the same counter should not be longer than the counter’s timeout.
The timeout of the 32-bit MIB counter depends on the object type and the port speed.
Packet counter timeout is calculated based on 64-byte packets and byte counter timeout is
calculated based on 1518 byte packets.
RX byte count: This counter is incremented once for every data byte of a received and forwarded
packet (includes both good and bad packets).
RX packet count: This counter is incremented once for every received and forwarded packet
(includes both good and bad packets).
TX byte count: This counter is incremented once for every data byte of a transmitted packet
(includes both good and bad packets).
TX packet count: This counter is incremented once for every transmitted packet (includes both
good and bad packets).
Drop packet count: This counter is incremented once for every drop of a received packet. Packet
drop events could be due to undersize, oversize, CRC error, lack of resources, local packet,
point-to-point control packet.