Cmsemicon CMS80F731 Series, Справочное руководство

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CMS80F731x Reference Manual
4.2 Related Registers
4.2.1
Oscillator Control Register CLKDIV
0x8F Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CLKDIV CLKDIV7 CLKDIV6 CLKDIV5 CLKDIV4 CLKDIV3 CLKDIV2 CLKDIV1 CLKDIV0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit0 CLKDIV<7:0>: System clock Fsys divider;
00H= Fsys=Fsys_pre;
Other =
Fsys=
Fsys_pre/
（
2*CLKDIV
）（
2,4... 510 division).
Modify the sequence of instructions required by CLKDIV (no other instructions can be inserted in the middle):
MOV TA,#0AAH
MOV TA,#055H
MOV CLKDIV,#02H
4.2.2
System Clock Switching Register SCKSEL
0xD6 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SCKSEL -- -- -- SALT WRITE CKSEL2 CKSEL1 CKSEL0
R/W R R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7 -- Forbidden Access.
Bit6~Bit5 -- Reserved, must be 0.
Bit4
SALT: System clock configuration selection;
1=
Based on the clock source configured > CKSEL < 2 :0 ;
0=
The clock source configured by CONFIG is the standard (power-up default selection).
Bit3 WRITE: Write enable, generate a pulse, perform clock switching;
1=
Switch clocks (you need to wait for the switching target clock source to stabilize bit set to
1 before you can write 1);
0= Do not switch clocks.
Bit2~Bit0
CKSEL<2:0>: System clock source select bit;
111= LSI;
110= LSE;
101= HSE;
100= HSI;
Other = Invalid value, access prohibited.
After the clock source is switched, the system will successfully switch within several system clock cycles, and it is
recommended that the program execute 6 NOPs before executing other instructions.
Modify the sequence of instructions required by SCKSEL (no other instructions can be inserted in between):
MOV TA,#0AAH
MOV TA,#055H
MOV SCKSEL,#05H