BAT32G1x9 user manual | Chapter 14 Watchdog timer
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14.4 Operation of the watchdog timer
14.4.1
Operational control of the watchdog timer
1)
When using the watchdog timer, set the following by option byte (000C0H):
•
The bit4 (WDTON) of the option byte (000C0H) must be set to "1" to allow the watchdog timer to run
count (after the reset is lifted, the counter starts to run) (see Article 33 for details). Chapter Options
Bytes).
WDTON
Watchdog timer counter
0
Disables counting runs (stops counting after de-reset).
1
Allow counting runs (start counting after de-reset).
•
The overflow time must be set by bit3~1 (WDCS2~WDCS0) of the option byte (000C0H) (see 14.4.2
and for14.4.2details Chapter 33).
•
The window opening period must be set by bit6 and bit5 (WINDOW1, WINDOW0) of the option bytes
(000C0H) (see 14.4.2 for details).14.4.2and Chapter 33).
2)
After the reset is lifted, the watchdog timer starts counting.
3)
After starting counting and before the overflow time set by the option byte, if you write "ACH" to the
allowed register (WDTE) of the watchdog timer, clear the watchdog timer and start counting again.
4)
Thereafter, writes to WDTE registers after the second time after the reset must be performed while the
window is open. If you write the WDTE register while the window is closed, an internal reset signal is
generated.
5)
If you do not write "ACH" to the WDTE register and exceed the overflow time, an internal reset signal is
generated. An internal reset signal is generated if:
•
When a bit manipulation instruction is executed on a WDTE register
•
When writing data other than "ACH" to the WDTE register
note
1.
Only when the allow register (WDTE
)
of the watchdog timer is written
for the
first
time after the reset is unchecked
,
regardless of the window opening period, as long as the WDTE is written at any time before the overflow time, the
watchdog timer is cleared and the count is restarted.
2.
From writing "ACH"
to
the WDTE
register
to clearing the watchdog timer counter, it is possible to generate
an
error of
up to
2
f
IL
clocks.
3.
The watchdog timer can be cleared before the count value overflows.
4.
As shown below, the watchdog timer operates in sleep or deep sleep mode depending on the setpoint of bit0
(WDSTBYON) of
the option byte (
000C0H).
WDSTBYON=0
WDSTBYON=1
Sleep mode
Stop the watchdog timer from
running.
Continue watchdog timer operation.
Deep sleep mode
When the WDSTBYON bit is "0", restart the watchdog timer count after the sleep or deep sleep mode is lifted.
At this point, the counter is cleared to "0" and the count begins.
