Cmsemicon BAT32G1 9 Series, Руководство пользователя

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BAT32G1x9 user manual | Chapter 6 Universal timer unit Timer4/8
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6.9.3 Operation as a multi-PWM output function
This is the function of extending the PWM function and using multiple slave channels for multiple PWM outputs
with different duty cycles.
For example, when 2 slave channels are used in pairs, the period and duty cycle of the output pulse can be
calculated using the following equation:
Note: WhenTDRmp(Subordinate1) setpoint >{TDRmnThe setpoint of (master).+1}or{TDRmq(Subordinate2), the setpoint}
＞
{TDRmnThe setpoint of (master).+1}when the duty cycle is exceeded100%, but for100%Output.
In interval timer mode, the timer count register mn (TCRmn) of the master channel runs and counts the cycles.
In single-pass count mode, the TCRmp register of slave channel 1 runs and counts the duty cycle and outputs the
PWM waveform from the TOmp pin. Starting with the INTMmn of the master channel, the value of the timer data
register mp (TDRmp) is loaded into the TCRmp register and decremented. If TCRmp becomes "0000H", INTMmp is
output and counts are stopped before the input next starts triggering (INTMmn of the master channel). After
generating INTMmn from the master channel and passing through a count clock, the output level of TOmp becomes
the effective level if TCRmp becomes "0000H" , which becomes invalid.
Like the TCRmp register for slave channel 1, in single count mode, the TCRmq register of slave channel 2 runs
and counts the duty cycle and outputs PWM from the TOmq pin Waveform. Starting with the INTMmn of the master
channel, the value of the TDRmq register is loaded into the TCRmq register and the count is decremented. If TCRmq
becomes "0000H", INTMmq is output and counts are stopped before the input next starts triggering (INTMmn of the
master channel). After generating INTMmn from the master channel and going through a count clock, the output level
of TOmq becomes effective if TCRmq becomes "0000H" , which becomes invalid.
When channel 0 is used as the master channel by such operation, up to three PWM signals can be output
simultaneously.
Note: To rewrite both the timer data register mn (TDRmn) of the master channel and the TDRmp
register
of
slave channel
1 at the same time, at least 2 write accesses are required. Because
the values of
the TDRmn registers and TDRmp
registers
are loaded into the TCRmn
registers and
TCRmp
registers
when the
master channel
generates
INTTMmn
, Therefore, if the intTMmn
is
rewritten before and after the main control channel is generated,
the
TOmp
pin cannot output the expected waveform. Therefore, to rewrite both the master's TDRmn register and the slave's
TDRmp
register at the same time, the
two
registers must be
rewritten immediately after the master channel
generates intTMmn (the same applies to the slave channel
).
2 TDRmq registers).
Note: m: Unit number (m=0,1)n: Master channel number (n=0, 2, 4).
p: Slave channel number q: Slave channel number
m=0Time:n
＜
p
＜
q≤3 (p
和
qis greater thanninteger)
m=1Time:n
＜
p
＜ q≤7 (p 和
qis greater thanninteger)
Pulse period = {TDRmn (master control) of the set value + 1}
×
counting time Clock cycle
Duty cycle 1[%] = setpoint for {TDRmp (slave 1)}/{TDRmn(master Control) of the set value +1}
×
100
Duty cycle 2[%] = setpoint for {TDRmq (slave 2)}/{TDRmn (primary Control) of the set value +1}
×
100