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5.1.3
Nested vectored interrupt controller
（
NVIC
）
The Nested Vectored Interrupt Controller (NVIC) is closely connected to the interface of the processor core, which can
realize low-latency interrupt processing and efficiently handle late-arriving interrupts. The nested vectored interrupt
controller manages interrupts including kernel exceptions.
◼
32 maskable interrupt channels( not including 16 Cortex®-M0 interrupt lines
）
；
◼
4 programmable priority levels (using 2-bit interrupt priority levels )
；
◼
Low-latency exception and interrupt handling
；
◼
Power management control
；
◼
Realization of system control register
；
The module provides flexible interrupt management functions with minimal interrupt delay.
5.2 Extended interrupt/ event controller (EXTI)
The extended interrupt/event controller includes 24 edge detection circuits that generate interrupts/event triggers. Each inp ut
line can be independently configured as an event or interrupt, as well as three trigger types of rising edge, falling edge or both
edges, and can also be independently shielded. The suspend register holds the interrupt request of the status line, and the
corresponding bit of the suspend register can be cleared by writing '1'.
5.3 Clock System
The clock of the device includes internal high-speed RC oscillator HSI (8 MHz), internal low-speed clock LSI (30 KHz),
external low-speed clock (32.768 KHz), PLL.
The system clock (SYSCLK) can choose the following clock sources:
◼
HIS oscillator clock
◼
PLL clock
◼
LSI oscillator clock
◼
LSE oscillator clock
2 secondary clock source
：
◼
30 Khz low-speed internal RC
，
which can be used as the clock source of IWDG, RTC, LPTIMER and LPUART.
Used to automatically wake up the system from STOP mode.
◼
32.768 KHz low-speed external crystal can be used as the clock source of RTC
、
LPTIMER and LPUART.
◼
When not in use, any clock source can be independently startup or shutdown to reduce system power
consumption.
The HSI clock is selected as the default system clock during reset. When needed, it is possible to take safe interrupt management
of the PLL clock (for example, when the indirect external oscillator fails).
