Evaluation Kit for CMX724x/CMX734x
PE0403
2014 CML Microsystems Plc
24
um0403/1
6.4.4. Generate Two External Digital Clocks
Configure the CMX7240/CMX7340 with the C-BUS register data given in Table 8.
Table 8 CMX7240/CMX7340 Register Settings
– External Digital Clocks
Write Data
C-BUS Register
Address
Name
$0021
$C0
Powerdown Control
$1900
$AB
System Clock 1 PLL Configuration
$E0C8
$AC
System Clock 1 Reference and Source Configuration
$0E00
$AD
System Clock 2 PLL Configuration
$E6C8
$AE
System Clock 2 Reference and Source Configuration
With the default 19.2MHz clock input, a digital clock frequency of 4.096MHz should be observed at the
system clock 1 output (TP4) and a frequency of 16.384MHz should be observed at the system clock 2
output (TP3).
Now write 0xC0C8 to either $AC or $AE registers, to turn off the system clock 1 or system clock 2 outputs,
respectively.
6.5.
Troubleshooting
After loading a Function Image
™ the ES0002xx application writes the activation code that has been typed
into the Activation Code edit box to the CMX7240/CMX7340 reference device. If this code is incorrect for
the Function Image
™ that has just been loaded, the CMX7240/CMX7340 will be locked and will not
respond to further input from the ES0002xx application. It is recoverable only by closing the ES0002xx
application, power cycling the PE0403 and PE0002 cards, and then restarting the application. Keep the
power off for at least 10 seconds during this process.
