Clevo W243HUQ Series, Руководство по обслуживанию

Страница: 63 / 99

Schematic Diagrams
CPU 7/7 (RESERVED) B - 9
B.Sch
e
m
a
tic D
iag
rams
CPU 7/7 (RESERVED)
V R E F _ C H _ A _ D I MM
R 4 0 * 0 _0 4
MV R E F _ D Q _ D I M 0
R 4 4 * 0 _0 4
M V R E F _ D Q_ D I M 1
Q 7
* A O3 4 0 2L
G
D S
R 28
1 K _ 1% _ 0 4
R 4 9
*1 K _ 0 4
R 29
1 K _ 1% _ 0 4
Q 6
* A O3 4 0 2L
G
D S
R 3 9
*1 K _ 0 4
R 3 1
1K _ 1 % _ 04
R 3 8
1K _ 1 % _ 04
D R A M R S T _ C N TR L [ 3, 14 ]
1 . 5 V
1 . 5 V
M V R E F _D Q_ D I MMA [ 9]
D R A M R S T _ C N TR L
D R A M R S T _ C N TR L
M V R E F _D Q_ D I MMB [ 10 ]
V R E F _ C H _ B _ D I MM
R
ESE
RVE
D
U 34 E
P Z 9 8 8 27 -3 6 4B - 01 F
C F G [ 0 ]
A K 2 8
C F G [ 1 ]
A K 2 9
C F G [ 2 ]
A L 2 6
C F G [ 3 ]
A L 2 7
C F G [ 4 ]
A K 2 6
C F G [ 5 ]
A L 2 9
C F G [ 6 ]
A L 3 0
C F G [ 7 ]
A M3 1
C F G [ 8 ]
A M3 2
C F G [ 9 ]
A M3 0
C F G [ 1 0]
A M2 8
C F G [ 1 1]
A M2 6
C F G [ 1 2]
A N 2 8
C F G [ 1 3]
A N 3 1
C F G [ 1 4]
A N 2 6
C F G [ 1 5]
A M2 7
C F G [ 1 6]
A K 3 1
C F G [ 1 7]
A N 2 9
R S V D 34
A M 3 3
R S V D 35
A J 2 7
R S V D 38
J 1 6
R S V D 42
A T 3 4
R S V D 39
H 16
R S V D 40
G 16
R S V D 41
A R 3 5
R S V D 43
A T 3 3
R S V D 45
A R 3 4
R S V D 56
A T 2
R S V D 57
A T 1
R S V D 58
A R 1
R S V D 46
B 3 4
R S V D 47
A 3 3
R S V D 48
A 3 4
R S V D 49
B 3 5
R S V D 50
C 35
R S V D 51
A J 3 2
R S V D 52
A K 3 2
R S V D 30
A E 7
R S V D 31
A K 2
R S V D 28
L 7
R S V D 29
A G 7
R S V D 2 7
J 1 5
R S V D 1 6
C 3 0 R S V D 1 5
D 2 3
R S V D 1 7
A 3 1
R S V D 1 8
B 3 0
R S V D 2 0
D 3 0
R S V D 1 9
B 2 9
R S V D 2 2
A 3 0
R S V D 2 1
B 3 1
R S V D 2 3
C 2 9
R S V D 2 4
J 2 0
R S V D 37
T 8
R S V D 6
B 4
R S V D 7
D 1
R S V D 8
F 2 5
R S V D 9
F 2 4
R S V D 1 1
D 2 4
R S V D 1 2
G2 5
R S V D 1 3
G2 4
R S V D 1 4
E 2 3
R S V D 32
W 8
R S V D 33
A T 2 6
R S V D 2 5
B 1 8
R S V D 44
A P 3 5
R S V D 1 0
F 2 3
R S V D 5
A J 2 6
V A X G_ V A L _ S E N S E
A J 3 1
V S S A X G_ V A L _ S E N S E
A H 3 1
V C C _ V A L _S E N S E
A J 3 3
V S S _ V A L _ S E N S E
A H 3 3
K E Y
B 1
V C C _ D I E _ S E N S E
A H 2 7
V C C I O_ S E L
A 1 9
R S V D 54
A N 3 5
R S V D 55
A M 3 5
C F G 6
C F G 5
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG[6:5]
R 92 *1 K _ 0 4
PCIE Port Bifurcation Straps
R 99 *1 K _ 0 4
On CRB
H_SNB_IVB#_PWRCTRL = low, 1.0V
H_SNB_IVB#_PWRCTRL = high/NC, 1.05V
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
CFG7
R 93 *1 K _ 0 4
C F G 7
3 . 3V [ 2, 3 , 1 1 , 13 , 1 4 , 1 5, 1 7 , 1 8, 19 , 2 0 , 22 , 2 3 , 2 6, 2 8 , 3 0, 3 1 , 3 3 , 34 , 3 5 ]
10/29
C F G 2
CFG2
C F G 4
CFG Straps for Processor
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
definition matches socket pin map definition
0:Lane Reversed
Display Port Presence Strap
1:(Default) Disabled; No Physical Display Port
attached to Embedded Display Port
0:Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG4
R 11 0 *1 K _ 0 4
R 11 1 *1 K _ 0 4
H _ C P U _ R S V D 1
H _ C P U _ R S V D 4
H _ C P U _ R S V D 3
H _ C P U _ R S V D 2
10/29
C F G 7
C F G 4
C F G 2
C F G 6
C F G 0
C F G 5
10/29
1 . 5V [ 3 , 6 , 9, 1 0 , 2 0, 2 6 , 2 8 , 31 , 3 3 ]
Sandy Bridge Processor 7/7
( RESERVED )
V R E F _ C H _A _ D I MM
V R E F _ C H _B _ D I MM
R 3 9 1 * 10 m i l_ 0 4
3 . 3 V
R 39 2 10 K _ 0 4
H _S N B _ I V B # _P W R C TR L
Sheet 8 of 43
CPU 7/7
(RESERVED)