Clevo W170HN, Руководство по обслуживанию

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Schematic Diagrams
CPU 7/7 (RESERVED) B - 9
B.Sch
e
m
a
tic D
iag
rams
CPU 7/7 (RESERVED)
C F G2
V R E F _ C H _A _D I MM
R 5 14 1 0K _ 1 % _ 04
3 . 3 V
H _ S N B _I V B #_ P W R C TR L
H _ C P U _ R S V D 2
H _ C P U _ R S V D 1
H _ C P U _ R S V D 4
H _ C P U _ R S V D 3
On CRB
H_SNB_IVB#_PWRCTRL = low, 1.0V
H_SNB_IVB#_PWRCTRL = high/NC, 1.05V
C FG 7
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
R 6 4 2 *0 _ 0 4
MV R E F _ D Q _D I M 0
R 6 4 3 *0 _ 0 4
C 3 67
0.
1u
_1
0V
_X
5R
_0
4
MV R E F _ D Q _ D I M 1
C F G 6
C F G 5
C F G4
C F G2
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CF G [6 :5 ]
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
definition matches socket pin map definition
0:Lane Reversed
C F G2
Sandy Bridge Processor 7/7 ( RESERVED )
PCIE Port Bifurcation Straps
C F G4
C F G7
RES
ER
VED
U 4 9 E
P Z 9 8 8 27 -3 6 4B -01 F
C F G [ 0 ]
A K 2 8
C F G [ 1 ]
A K 2 9
C F G [ 2 ]
A L 2 6
C F G [ 3 ]
A L 2 7
C F G [ 4 ]
A K 2 6
C F G [ 5 ]
A L 2 9
C F G [ 6 ]
A L 3 0
C F G [ 7 ]
A M 3 1
C F G [ 8 ]
A M 3 2
C F G [ 9 ]
A M 3 0
C F G [ 1 0]
A M 2 8
C F G [ 1 1]
A M 2 6
C F G [ 1 2]
A N 2 8
C F G [ 1 3]
A N 3 1
C F G [ 1 4]
A N 2 6
C F G [ 1 5]
A M 2 7
C F G [ 1 6]
A K 3 1
C F G [ 1 7]
A N 2 9
R S V D 3 4
A M 33
R S V D 3 5
A J 2 7
R S V D 3 8
J 1 6
R S V D 4 2
A T 3 4
R S V D 3 9
H 16
R S V D 4 0
G 16
R S V D 4 1
A R 35
R S V D 4 3
A T 3 3
R S V D 4 5
A R 34
R S V D 5 6
A T 2
R S V D 5 7
A T 1
R S V D 5 8
A R 1
R S V D 4 6
B 3 4
R S V D 4 7
A 3 3
R S V D 4 8
A 3 4
R S V D 4 9
B 3 5
R S V D 5 0
C 35
R S V D 5 1
A J 3 2
R S V D 5 2
A K 3 2
R S V D 3 0
A E 7
R S V D 3 1
A K 2
R S V D 2 8
L 7
R S V D 2 9
A G 7
R S V D 2 7
J 1 5
R S V D 1 6
C 3 0 R S V D 1 5
D 2 3
R S V D 1 7
A 3 1
R S V D 1 8
B 3 0
R S V D 2 0
D 3 0
R S V D 1 9
B 2 9
R S V D 2 2
A 3 0
R S V D 2 1
B 3 1
R S V D 2 3
C 2 9
R S V D 2 4
J 2 0
R S V D 3 7
T 8
R S V D 6
B 4
R S V D 7
D 1
R S V D 8
F 2 5
R S V D 9
F 2 4
R S V D 1 1
D 2 4
R S V D 1 2
G 2 5
R S V D 1 3
G 2 4
R S V D 1 4
E 2 3
R S V D 3 2
W 8
R S V D 3 3
A T 2 6
R S V D 2 5
B 1 8
R S V D 4 4
A P 3 5
R S V D 1 0
F 2 3
R S V D 5
A J 2 6
V A X G_ V A L _ S E N S E
A J 3 1
V S S A X G_ V A L_ S E N S E
A H 3 1
V C C _ V A L _S E N S E
A J 3 3
V S S _ V A L _ S E N S E
A H 3 3
K E Y
B 1
V C C _D I E _ S E N S E
A H 27
V C C I O_ S E L
A 1 9
R S V D 5 4
A N 35
R S V D 5 5
A M 35
R 5 1 6 *1 0 m il _ s ho rt
10/21
H _ S N B _ I V B # _ P W R C T R L _ R
C F G7
CFG Straps for Processor
3 . 3V 2 , 3 , 1 1 , 1 2, 1 6 , 1 8 , 19 , 2 0 , 2 2, 2 3 , 2 4 , 25 , 2 7 , 2 8, 29 , 3 0 , 3 3, 3 5 , 3 7 , 38 , 3 9
C F G5
Display Port Presence Strap
1:(Default) Disabled; No Physical Display Port
attached to Embedded Display Port
0:Enabled; An external Display Port device is
connected to the Embedded Display Port
C F G4
V R E F _C H _ A _ D I MM
R 1 5 9
1 K _ 1% _ 0 4
R 50 0 *1 K _ 0 4
Q9
*A O 3 40 2 L
G
D S
R 4 9 1 * 1K _0 4
R 15 3
* 1K _0 4
Q1 0
*A O 3 40 2 L
G
D S
R 1 6 0
1 K _ 1% _ 0 4
R 14 9
* 1K _0 4
R 1 5 5
1K _ 1 % _ 04
R 49 2 *1 K _ 0 4
R 4 9 3 * 1 K _0 4
R 5 0 3 * 1 K _0 4
R 1 5 0
1K _ 1 % _ 04
1 . 5 V
1 . 5V
D R A M R S T _ C N T R L 3 , 1 9
D R A MR S T _C N T R L 3, 1 9
1 . 5V 3 , 6 , 9, 10 , 2 5 , 2 9, 3 3 , 3 5 , 37 , 3 8
C F G0
C 3 5 7
0.
1u_1
0V
_X
5R
_0
4
10/21
MV R E F _ D Q _D I MM A 9
R 2 5 4 0 _ 04
C F G6
MV R E F _ D Q_ D I M MB 10
R 2 7 7 0 _ 04 V R E F _ C H _B _D I MM
V R E F _C H _ B _ D I MM
Sheet 8 of 49
CPU 7/7
(RESERVED)