Schematic Diagrams
CLOCK GENERATOR B - 17
B.Sch
e
m
a
tic D
iag
rams
CLOCK GENERATOR
3 .3VS
3 .3VS
3.3 VS
3 .3VS_C LK
3. 3VS
3 .3VS
3 .3VS
3. 3VS
C LK_PWRG D
14
CL K_ BSEL1 4
PM_STPPCI#
1 4
PM_STPCPU#
1 4
NEWC AR D_C LKREQ# 17
WL AN _CL KR EQ # 17 ,23
C LK_BSEL2
4
CL K_ BSEL 0
4
MCH_ CLKREQ# 5
PWRSAVE# 14
CL K_PCIE_I CH 13
CL K_DREFSS# 5
CL K_PCIE_G LAN# 2 3
CL K_PCIE_MINI
17
CL K_DREF# 5
CL K_PCIE_3 GPLL# 5
CL K_PCIE_G LAN 23
CL K_MCH _BCLK 4
CL K_PCIE_N EW _CARD 1 7
CL K_IC H14
1 4
CL K_PCIE_N EW _CARD # 17
CL K_PCIE_MINI # 17
CL K_DREF 5
CL K_SATA# 12
CLK_I CH48
1 4
CL K_CPU_ BC LK 2
CL K_DREFSS 5
CL K_CPU_ BC LK# 2
CL K_SATA 1 2
CL K_PCIE_3 GPLL 5
CL K_MCH _BCLK# 4
CL K_PCIE_I CH# 1 3
PCL K_IC H
1 3
IC H_SMBCL K0
9,1 0,1 4
IC H_SMBDAT0
9,1 0,1 4
PCL K_TPM
17
PC LK_KBC
2 2
PCLK_C AR D
1 9
PC LK_13 94
1 8
CLK_4 8M_C ARD
19
CL K_PCIE_MINI _3G # 23
CL K_PCIE_MINI _3G 2 3
3 .3VS
2,5 ,8. .1 5,1 7.. 26, 31
LAN_CL KREQ# 23
Z16 04
Z16 11
C LK_CPU_ BC LK#
Z16 34
Z16 18
C LK_SATA
C LK_PCI E_ ICH
C LK_DR EF
Z16 23
C LK_SATA#
FSLA
Z16 25
Z16 29
Z16 14
Z16 24
C LK_DR EFSS
C LK_PCI E_ MIN I#
Z160 9
Z160 7
Z16 05
Z16 27
Z16 26
C LK_MC H_BCL K#
PCLK_ CARD
XTAL _OUT
C LK_PCI E_ NEW_CAR D
Z16 35
C LK_PCI E_ GLAN
C LK_PCI E_ MIN I
Z16 30
Z1 601
Z16 17
C LK_PCI E_ NEW_CAR D#
Z16 13
Z16 31
C LK_PCI E_ 3GPLL
C LK_PCI E_ GLAN#
Z16 36
Z16 15
Z16 22
Z16 28
FSLB
Z16 33
C LK_IC H48
C LK_DR EFSS#
C LK_CPU_ BC LK
Z16 21
Z16 32
Z16 12
C LK_PCI E_ 3GPLL #
C LK_PCI E_ ICH #
C LK_DR EF#
C LK_MC H_BCL K
PCLK_ KBC
Z16 16
Z16 03
REF_1 4.3 18M
Z16 02
CLK_I CH1 4
FSLC
Z160 6
PCLK_ ICH
Z160 8
Z16 20
Z16 19
PCLK_ 139 4
CLK_4 8M_ CARD
C LK_PCI E_ MIN I_3 G
C LK_PCI E_ MIN I_3 G#
CLK_ PW RGD_ T
XTAL _IN
Z1 610
C 110
1 u_6 .3V_0 4
R N5
3 3_4 P2R_0 4
1
4
2
3
R58
0_0 4
X1
FSX8L _14. 31 8MHz
1
2
3
4
R 321
0 _04
L2 0
HC B1 608 KF- 121 T25
L23
HCB1 608 KF- 121 T25
L 21
HCB16 08KF-1 21T25
C6 5
10u _10 V_ 08
R7 0
1 0K_04
R N9
3 3_4 P2R_0 4
1
4
2
3
R4 9
2.2 K_ 04
R5 5
12_ 06
R N13
3 3_4 P2R_0 4
1
4
2
3
R 65
100 K_ 04
R N17
3 3_4 P2R_0 4
1
4
2
3
R N3
3 3_4 P2R_0 4
1
4
2
3
R41
300 _1%_0 4
R5 2
12_ 06
C44 6
0. 1u_ 10V_X7R_ 04
R3 7
47 5_1 %_ 04
C 492
0 .1u _10 V_X7 R_04
C482
0.1 u_1 0V_X7 R_0 4
C 487
1 u_6 .3V_ 04
R N24
3 3_4 P2R_0 4
1
4
2
3
C45 6
1u_ 6.3 V_04
R 40
1K_1%_0 4
R N21
3 3_4 P2R_0 4
1
4
2
3
C 158
2 2p_ 50V_ 04
R 61
33 _04
R3 28
1 0K_04
R5 3
10K_0 4
C4 76
0 .1u _10 V_ X7R _04
R32 9
0_0 4
C46 1
0. 1u_ 10V_X7R_ 04
R N2
3 3_4 P2R_0 4
1
4
2
3
R N20
3 3_4 P2R_0 4
1
4
2
3
R5 9
1 0K_04
R7 1
1 0K_04
R60
3 3_04
U1
IC S9 LPR36 3DG LF
5
11
56
62
4 9
5 1
3 5
4 8
5 2
2
6
8
55
1 6
61
12
42
3 4
58
57
45
3 6
3 3
60
3
4
28
50
54
9
64
13
21
37
53
3 2
3 0
3 1
2 7
2 6
2 4
2 5
2 3
2 2
1 9
2 0
1 8
1 7
1 4
1 5
10
47
7
1
29
46
3 9
3 8
4 1
4 0
4 4
4 3
59
63
PCICL K3/*SELPCI EX0_L CD#
VDD48
VD
D
R
EF
CPU_STOP#
C PUT_L 1F
C PU C_L 0
PCIe C_L 5
CPUC_L 1F
C PU T_L 0
GN
D
GN
D
PCICL K_F4/I TP_EN
SDATA
FSL B/ TEST_MODE
REF1/FSLC /TEST_SEL
FSL A/ USB_48 MHz
V
DDP
C
IE
X
*PWRSAVE#
X1
X2
VDDA
PCIe T_L 5
*PEREQ4 #
REF0_1 4.3 18M
PCICL K1
PCICL K2
VD
D
P
C
IE
X
V
DDCP
U
SCLK
*SEL LCD_ 27# /PCI CLK_F5
**PC ICL K0 /REQ_ SEL
GN
D
V
DDP
C
I
E
X
GN
D
GN
D
*PEREQ3 #
PCIe T_L 4
PCIe C_L 4
SATACLKC_ L
SATACLKT_ L
PCIe T_L 3
PCIe C_L 3
PCIe C_L 2
PCIe T_L 2
PCIe T_L 1
PCIe C_L 1
2 7SS/LCD _SSCGC/ PCIe C_L 0
2 7FIX/ LCD _SSCGT/ PCIe T_L 0
PC IeT_L9 /DO TT_ 96MH zL
PC IeC _L9 /DO TC_ 96MH zL
VTT_ PW R_GD /PD#
VR
E
F
VD
D
P
C
I
VD
D
P
C
I
GN
D
GN
D
A
PCIe T_L 6
PCIe C_L 6
PCIe T_L 7/PEREQ1 #
PCIe C_L 7/PEREQ2 #
PCI eT_ L8/ CPUITPT_L 2
PCI eC_ L8/ CPUI TPC_L 2
GN
D
PCI/ PC IEX_ STOP#
R N16
3 3_4 P2R_0 4
1
4
2
3
C 145
1 0u_ 10V_0 8
C 157
2 2p_ 50V_0 4
R63
3 3_04
C6 6
10 u_1 0V_08
R N1
3 3_4 P2R_0 4
1
4
2
3
R3 8
47 5_1 %_ 04
R 62
33 _04
R64
33_ 04
C4 71
0. 1u_ 10V_X7R_ 04
C4 81
0. 1u _10 V_ X7R _04
C1 51
*0. 1u_ 10V_ X7R_ 04
R5 6
33_ 04
Insatlled: Differential clock
level is higher
PEREQ1#: P CIECLK 0, 6
PEREQ2#: P CIECLK 1, 8
PEREQ3#: P CIECLK 2, 4
PEREQ4#: P CIECLK 3, 5, 7
PEREQ[1..4]# have
internal pull up
? ? ? !
CLOCK GENERATOR
Layout note:
Layout note:
PLACE CRYSTAL WITHIN 500
MILS OF ICS9LPR363
30mi ls
40mil s
20mi ls
B SEL0
1
8 00 MHz
5 33 MHz
0
Host Clo ck
BSEL 1
0
BSEL 2
F requ enc y
13 3 M Hz
20 0 M Hz
6-02-09363-E61
6-22-14R31-1BK
6-19-31001-164-1
6-16-33034-45C
0
1
0
RTM 875 T-36 3
6-0 2-8 7536 -EL0
Sheet 16 of 38
CLOCK
GENERATOR
Содержание TN120R
Страница 1: ......
Страница 2: ......
Страница 3: ...Preface I Preface Notebook Computer TN120R Service Manual ...
Страница 42: ...Disassembly 2 18 2 Disassembly ...
Страница 48: ...Part Lists A 6 Combo TN120R A Part Lists Combo TN120R Figure A 4 Combo TN120R 寬降低 無鉛 無鉛 無鉛 無鉛 ...
Страница 50: ...Part Lists A 8 HDD TN120R A Part Lists HDD TN120R Figure A 6 HDD TN120R 無鉛 無鉛 ...
Страница 90: ...Schematic Diagrams B 40 B Schematic Diagrams ...