Clevo M540V, Руководство по обслуживанию

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Schematic Diagrams
B - 12 CLOCK GENERATOR, CCD
B.Schematic Diagrams
CLOCK GENERATOR, CCD
+5V +VCC_CCD
+3VS
+2.5VS
+3VS
+VCCP
+3VS
+3VS
+3VS
+3.3VCLK
+VCC_CCD
+3VS
CCD_PWREN 23
CLK_CPU_FSB 2
CLK_CPU_FSB# 2
SMB_SBDATA 9,16
SMB_SBCLK 9,16
SB_OSCCLK 16
GCLK_NB 6
VLINKCLK 17
USB_CLK 15
DDRCLK#3 9
DDRCLK3 9
DDRCLK0 9
DDRCLK#2 9
DDRCLK2 9
DDRCLK#0 9
DDRCLK#1 9
DDRCLK1 9
CLK_NB_FSB# 4
CLK_NB_DAO 5
CLK_NB_DAI 5
GUICLK 6
PCISBCLK 17
APICCLKSB 17
PCLK_PCM 27
PCLK_H8 23
PCLK_MPCI 18
PCLK_LPC 21
PCISTOP# 16
CPUSTP# 16,31
PCLK_1394 22
CLKEN# 31
USB_PN5 15
USB_PP5 15
CLK_NB_FSB 4
CPUBSELSB 16
Z1124
Z1120
Z1122
Z1119
Z1117
Z1123
Z1116
Z1118
Z1121
+3.3VCLK
Z1102
Z1106
Z1103
Z1101
Z1114
Z1115
Z1112
Z1113
Z1137
MODE
SEL_CPU
PCI_STOP
SEL_SD_DDR
MULTSEL0
Z1109
Z1110
Z1111
CPU_STOP
GUICLK
GCLK_NB
VLINKCLK
USB_CLK FS2
APICCLKSB
PCISBCLK
FS0
FS3
Z1105
Z1107
Z1108
FS1
FS0
FS3
SEL_CPU
MODE
MULTSEL0
SEL_SD_DDR
PCLK_PCM
CLK_MCH_FSB
CLK_MCH_FSB#
CLK_CPU_FSB
CLK_CPU_FSB#
PCLK_H8
PCLK_MPCI
GUICLK
USB_CLK
GCLK_NB
VLINKCLK
PCLK_LPC
APICCLKSB
PCISBCLK
PCLK_PCM
PCLK_H8
PCLK_MPCI
CPU_STOP
PCI_STOP
FS1
Z1104 +3.3VCLK
CPUBSEl_1
USB_PP5
USB_PN5
Z1136
Z1135
PCLK_LPC FS1
CPUBSEl_0
CLOCK_SW
CPUBSEl_0
Z1125
CPUBSEl_1
FS2
R437 10K_04
C285
10u_08
R164 33_04
R150 22_04
C228
0.01u_04
C278
10u_08
C271 10p_04
R167 22_04
R155 22_04
SW4
SW-4X2_4
1 2
4 3
C244
0.01u_04
R178 22_04
R193
10K_04
R152 *33_04
C273 10p_04
R162 51_1%
R444 *10K_04
R440 *10K_04
L6
HCB2012K-500T40
R189 22_04
C257 10p_04
R173 51_1%
C272
0.01u_04
L22
HCB1608K-121T25
R148 22_04
R177 51_1%
R445 10K_04
R182 33_04
C899
*0.01u_04
D10 *1SS355 A C
C251 10p_04
R438 22_04
Q88
2N3906
B
E
C
R142 22_04
Q19
2N7002
G
D
S
Q87
2N3904
B
E
C
R175 10K_04
C293
10u_08
R439 10K_04
R153 22_04
R442 22_04
Q32
2N3904
B
E
C
C738
10p
R158 22_04
C259
0.1u_04
C248 10p_04
R145
475_1%
D9 *1SS355 A C
R192
4.7K_04
U13
ICS950902
56
1
25
26
5
16
22
23
51
55
34
40
50
2
9
13
19
24
33
39
47
54
20
21
32
31
30
29
3
4
6
7
8
10
11
12
14
15
17
18
36
35
38
37
42
41
44
43
46
45
49
48
53
52
27
28
VttPWRGD#REF1
FS0/REF0
IREF
(PD#)RESET#
VDDAGP
VDDPCI
VDD48M
AVDD
VDDCPU
VDDREF
VDD3.3/2.5
VDD3.3/2.5
VDDI
GND
GND
GND
GND48M
AGND
GND
GND
GNDI
GND
FS3/48M
FS2/24_48M
DDRT4/SDRAM8
DDRC4/SDRAM9
DDRT5/SDRAM10
DDRC5/SDRAM11
X1
X2
MODE/AGP0
SEL_CPU/AGP1
(PCI_STOP#)AGP2
FS1/PCICLK_F
SEL_SD_DDR#/PCICLK0
MULTDEL0/PCICLK1
PCICLK2
PCICLK3
PCICLK4
(CPU_STOP#)PCICLK5
DDRT3/SDRAM6
DDRC3/SDRAM7
DDRT2/SDRAM4
DDRC2/SDRAM5
DDRT1/SDRAM2
DDRC1/SDRAM3
DDRT0/SDRAM0
DDRC0/SDRAM1
FBOUT
BUFFER_IN
CPUCLK_PPC
CPUCLK_PPT
CPUCLKST/CPUCLKT
CPUCLKSC/CPUCLKC
SCLK
SDATA
R191 *0_04
C544
0.1u_04
R174 33_04
R640 0
Q24
AO3409
G
D S
R151 33_04
R183 51_1%
R443
10K_04
R176 33_04
R436 10K_04
C723 10p_04
R441
2.2K_04
R195 22_04
C735
10p
C235
0.01u_04
JCCD-1
85205-0500
1
2
3
4
5
R196
4.7K_04
R159 22_04
C288
1u
R161 22_04
C263
0.01u_04
C733
0.01u_04
C715 10p_04
X3
14.318MHz
1
2
R143 10K_04
R649
2.2K_04
R653 4.7K_04
R639 0
R160 22_04
R435 10K_04
C726 10p_04
R147 22_04
R64
100K_04
R197
220
R149 22_04
L21 HCB2012K-500T40
C543
10u_08
L39
*PLW3216S161SQ2
1
4
2
3
R156 22_04
C731 10p_04
C227
0.01u_04
C242
0.1u_04
R144 22_04
C241 10p_04
FROM H8 def HI
CCD
CLOCK GENERATOR
FS1=1 CPU=133 AGP=66 PCI =33
FS1=0 CPU=100 AGP=66 PCI =33
CO-LAYOUT
CPU SELEC S/W
100 133 MHz MHz SW4
SW4-1
SW4-2 ON
ON
OFF
SW DEF. OFF
PLACE IN BOTTOM SIDE CLOSE
MINI-PCI
OFF
SB
CLOCK
Sheet 11 of 41
CLOCK
GENERATOR, CCD