Schematic Diagrams
B - 18 Clock Generator & Clock Buffer
B.Schematic Diagrams
Clock Generator & Clock Buffer
C LK _ S A T A
C L K _ S A T A _ R
R N 1 1
4 P 2 R X 0 _ 0 4
1
4
2
3
1
M _ C L K _ D D R 3
R 2 7 3
*3 3 _ 0 4
L 2 4
H C B 1 0 0 5 K F -1 2 1 T 2 0
C L K B U F _ A V D D
M_ F W D S D C L K OA _ D
5
P C I E _ C L K _ H D V # 1 8
P C I E _ C L K _ N B 4
H _ C L K _ N B _ R
Frequency
C L K E N #
2 8
M_ C L K _ D D R 0 # _R
P C I E _ C L K _ N E W # _ R
R 1 2 7
*0 _ 0 4
P C I E _ C L K _ S B _ R
C 5 13
1 U _6 . 3 V _0 4
M _ C L K _ D D R 2 1 0
P C L K _ K B C
C 2 99
0 . 1 u _ 1 6V _ 04
3 . 3 V S
Mobile mode
C L K G E N _ V D D A
R N 3 2
4 P 2 R X 3 3 _ 0 4
1
4
2
3
R 2 7 2
33 _ 0 4
0
P C I E _ C L K _ N E W # 2 2
P C I E _ C L K _ N E W _ R
PCICLK3
0
P C I E _ C L K _ M I N I 2 2
C 3 0 0
0 . 1 u _ 1 6 V _ 0 4
C L K _ 1 4 M_ 6 7 1 M X 6
R N 1 3
4 P 2 R X 0 _ 0 4
1
4
2
3
Place CRYSTAL Within 500
mils of ICS9LPR600
S T P _ P C I #
C 51 9
* 1 0 p_ 5 0 V _ 0 4
R 2 7 5
*3 3 _ 0 4
3. 3V S
Z 1 7 0 7
3 . 3 V S
0
M_ C L K _ D D R 1 _ R
C 5 14
0 . 1 u _ 1 6V _ 04
1
S U S B #
2 0 , 2 1 , 2 2 , 2 6 , 2 7, 30 , 3 1
P E C L K R E Q 0 #
M _ C L K _ D D R 0 9
M _ C L K _ D D R 3 1 0
Pin 1
BSEL1
M o d i f y C 5 0 9 , C 5 1 0 f r o m 3 3 P F c h a n g e t o 2 7 P F f o r O S C i s s u s e .
M_ C L K _ D D R 2 # _R
P C L K _ D E B U G_ R
P C I E _ C L K _ M I N I # 2 2
R 2 7 6
*3 3 _ 0 4
M _ C L K _ D D R 0 #
M_ C L K _ D D R 3 _ R
C L K GE N _ F S L1
100 MHz
H _ C LK _ C P U # 2
P C I E T _ L 1
C P U _ B S E L 0 2
Z _ C L K 1 _ R
R 28 2
* 2 . 7 K _ 0 4
CLK_STOP#
0
Z _ C L K 0
C 2 9 3
0 . 0 1u _ 1 6 V _ X 7 R _ 0 4
P C I E _ C L K _ S B # 1 4
0
U 1 4
I C S 9 P 9 3 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
D D R C 0
D D R T 0
V D D 1 . 8
D D R T 1
D D R C 1
G N D
V D D A 1 . 8
G N D
C L K _ I N T
C L K _ I N C
V D D 1 . 8
D D R T 2
D D R C 2
G N D
G N D
D D R C 5
D D R T 5
V D D 1 . 8
G N D
D D R C 4
D D R T 4
V D D 1 . 8
S D A T A
S C L K
F B _ I N
F B _ OU T
D D R T 3
D D R C 3
R 2 7 1
22 _ 0 4
C L K GE N _ F S 4
H _ C LK _ N B #
4
Mode
H _ C L K _ C P U #_ R
R N 3 4
4 P 2 R X 3 3 _ 0 4
1
4
2
3
C 4 9 9
0 . 1 u _ 1 6 V _ 0 4
1
M _ C L K _ D D R 1
P C I E _ C L K _ H D V # _ R
M _ F W D S D C LK OA _ D #
5
C 50 1
1 U _ 6 . 3 V _ 0 4
R N 3 0
4 P 2 R X 3 3 _ 0 4
1
4
2
3
PECLKREQ1#
C L K _ S A TA # 1 5
C LK _ S A T A #
P C L K _ L P C R O M
166 MHz
3 . 3 V S
C L K GE N _ M OD E
R N 2 9
4 P 2 R X 3 3 _ 0 4
1
4
2
3
R N 2 7
4 P 2 R X 3 3 _ 0 4
1
4
2
3
CPU_STOP#
R 2 5 1
33 _ 0 4
C L K _ S A TA
1 5
M_ C L K _ D D R 0 _ R
200 MHz
M_ C L K _ D D R 1 # _R
C 5 0 4
1 0 U _ 1 0 V _ 0 8
C 3 0 1
0 . 1 u _ 1 6 V _ 0 4
L 2 3
H C B 1 0 05 K F -1 2 1 T2 0
Pin 17
0
P C I E _ C L K _ N E W
22
VTTOWRGD/PD#
C L K GE N _ F S L2
C L K GE N _ F S 3
R 2 5 3
33 _ 0 4
Z _ C L K 1
1 3
M _ C L K _ D D R 2 #
R 2 7 4
33 _ 0 4
0
M _ C L K _ D D R 3 # 1 0
Z 1 7 0 6
C LK _ 14 M _ 6 71 M X
PECLKREQ0#
1
C L K _ P C I E _ J M3 8 0 # 2 0
C LK _ 12 M _ U S B
PCICLK5
R 2 7 0
22 _ 0 4
C L K _ 1 4 M_ 3 0 7 E L V 1 8
S T P _ P C I #
C P U _ B S E L 2 2
C L K GE N _ F S L2
C L K E N
R N 2 6
4 P 2 R X 3 3 _ 0 4
1
4
2
3
133 MHz
R 2 8 5
0_ 0 4
C 5 0 9
2 7 p _ 5 0V _ 04
Pin 16
0
P C I E _ C L K _ N B #_ R
H _ C LK _ C P U 2
M_ C L K _ D D R 3 # _R
C L K GE N _ F S L0
M _ C L K _ D D R 0 # 9
M _ C L K _ D D R 0
R 2 6 8
1 0 K _ 0 4
R N 1 0
4 P 2 R X 0 _ 0 4
1
4
2
3
(LO)Non-STUFF
Pin 28
BSEL2
C P U _ B S E L 1 2
1
1 . 8 V S
C L K B U F _ A V D D
MI N I _ C A R D _ C L K R E Q # 2 2
Z _ C L K 0 _ R
R 2 7 7
0_ 0 4
PCI_STOP#
C L K B U F _ V D D
M _ C L K _ D D R 2 # 1 0
C L K _ S A T A # _ R
C LK _ 14 M _ 3 07 E LV
C 5 1 0
2 7 p_ 5 0 V _ 0 4
R N 1 2
4 P 2 R X 0 _ 0 4
1
4
2
3
1 . 8 V S
C L K _ 1 2 M_ U S B
1 5
H _ C LK _ N B
4
R 1 29
2 2 _ 0 4
M_ C L K _ D D R 2 _ R
P C L K _ S B
U 1 5
I C S 9 L P R 6 0 0 C GL F
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
5 6
5 5
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
( C L K _ S T O P # )/ V T T P W R G D / P D #
V D D R E F
* *F S L 0 / R E F 0 _ 2x
*F S L 1 / R E F 1 _ 2x
X1
X2
G N D R E F
G N D P C I
** F S L 2 / P C I C L K 0_ 2 x F
* *F S 3 / P C I C L K 1_ 2 x F
* *F S 4 / P C I C L K 2
* (P C I _ S T OP #) / P C I C L K 3
G N D P C I
V D D P C I
** MO D E / P C I C L K 4
(P E C L K R E Q 0 #) / P C I C L K 5
(P E C L K R E Q 1 #) / P C I C L K 6
P C I C L K 7
V D D P C I
G N D Z
Z C L K 0
Z C L K 1
V D D Z
V D D 4 8
1 2 MH z
** S E L 2 4 _ 48 # / 2 4 _ 4 8 MH z
G N D 4 8
* (C P U _ S TO P # )/ R E S E T #
V D D C P U
C P U T_ L 0 F
C P U C _ L 0 F
G N D C P U
C P U T _ L1
C P U C _ L1
V D D A
S A T A C LK T _L
S A T A C L K C _L
G N D A
S C L K
S D A TA
P C I E T _ L0
P C I E C _ L0
G N D P C I E X
P C I E T _ L1
P C I E C _ L1
V D D P C I E X
P C I E T _ L2
P C I E C _ L2
P C I E T _ L3
P C I E C _ L3
P C I E T_ L 4 F
P C I E C _ L 4 F
G N D P C I E X
P C I E T_ L 5 F
P C I E C _ L 5 F
V D D P C I E X
R 25 7
2 . 2 K _ 1 % _ 0 4
R 2 5 4
33 _ 0 4
Desktop mode
S _ C L K
9 , 1 0 , 1 4 , 2 2
BSEL0
N E W _ C A R D _ C L K R E Q # 2 2
R N 3 1
4 P 2 R X 3 3 _ 0 4
1
4
2
3
C 2 95
0 . 1 u _ 1 6V _ 04
C L K _ 1 4 M_ 9 6 8 1 4
Z 17 0 5
P E C L K R E Q 1 #
Z _ C L K 1
C L K GE N _ F S L0
3 . 3 V S
2, 6, 10 , 1 1 , 1 3 , 1 4 , 1 5 , 1 6 , 1 8, 19 , 2 0 , 2 1 , 2 2 , 2 3 , 2 4 , 2 5, 26 , 2 7 , 2 8
P C L K _ S B 1 3
P C I E _ C L K _ H D V
1 8
R 28 3
1 0 K _ 0 4
R 1 2 8
*0 _ 0 4
R 2 6 4
* 0 _ 0 4
C L K GE N _ F S 3
R 2 7 8
33 _ 0 4
C 4 9 4
1 0 U _1 0 V _ 0 8
FS4
P C I E _ C L K _ N B # 4
C 50 6
0 . 1 u _ 16 V _0 4
P C I E _ C L K _ MI N I _ R
H _ C L K _ C P U _R
C 4 98
0 . 1 u _ 1 0V _ X7 R _ 0 4
P C L K _ L P C R O M
R 25 0
2 . 2 K _ 1 % _ 0 4
C 2 9 2
0. 1u _ 1 0 V _ X 7 R _ 0 4
3 . 3 V S
P C I E _ C L K _ H D V _ R
S _ D A T
9 , 1 0 , 1 4 , 2 2
P C I E _ C L K _ S B # _ R
C L K GE N _ F S L1
P C L K _ K B C 2 1
P C I E _ C L K _ N B _R
C L K GE N _ F S 4
L 4 7
H C B 1 0 0 5 K F - 12 1 T 2 0
0
R N 2 8
4 P 2 R X 3 3 _ 0 4
1
4
2
3
C L K _ P C I E _ J M3 8 0 2 0
P C I E C _ L 1
C 5 0 2
0 . 1 u _ 1 6 V _ 0 4
1
P C I E _ C L K _ S B
1 4
C L K GE N _ V D D
S _ D A T
9, 10 , 1 4 , 2 2
C P U S T P #
6
(HI)PULLl-UP
0
1 . 8 V S
4, 5, 6, 7, 13 , 1 4 , 1 5 , 1 6 , 1 8 , 2 7
C LK _ 14 M _ 9 68
X3
1 4 . 3 18 M H z
1
2
M _ C L K _ D D R 2
R 28 1
2 . 7 K _ 0 4
1
S E L2 4 _ 4 8 #
RESET#
3 . 3 V S
R N 3 3
4 P 2 R X 3 3 _ 0 4
1
4
2
3
H _ C L K _ N B # _ R
R 28 8
2 . 2 K _ 1 % _ 0 4
Pin 12
Z _ C L K 0
6
F B _ I N A
M _ C L K _ D D R 1 #
M _ C L K _ D D R 3 #
R 28 7
* 1 0 K _ 04
C 2 9 4
0 . 1 u _ 1 6 V _ 0 4
Host Clock
F B _ OU T A
1
C L K _ 1 2M _ U S B _ R
C 2 9 8
1 0 U _ 1 0 V _ 0 8
Clock Generator Pin 15
1
S _ C L K
9, 10 , 1 4 , 2 2
M _ C L K _ D D R 1 # 9
C 3 02
1 0 p _ 50 V _0 4
L 4 6
H C B 1 00 5 K F -1 21 T 2 0
Q 1 9
2 N 7 0 02 W
G
D
S
C 2 8 6
1 0 U _ 10 V _ 0 8
PCICLK6
P C I E _ C L K _ MI N I # _ R
Status
1
M _ C L K _ D D R 1 9
C L K GE N _ M OD E
Z 1 7 0 4
C 5 0 0
0 . 0 1 u _ 1 6V _ X7 R _ 0 4
FS3
Sheet 17 of 37
Clock Generator &
Clock Buffer
Содержание M540SS
Страница 1: ......
Страница 2: ......
Страница 3: ...Preface I Preface Notebook Computer M540SS M548SS M549SS Service Manual...
Страница 54: ...Part Lists A 10 Bottom M549SS A Part Lists Bottom M549SS Figure A 8 Bottom M549SS...
Страница 55: ...Part Lists LCD M540SS A 11 A Part Lists LCD M540SS EMI 3 5MM 0 3MM M540S M540S Figure A 9 LCD M540SS...
Страница 56: ...Part Lists A 12 LCD M549SS A Part Lists LCD M549SS EMI 3 5MM 0 3MM M540S M540S Figure A 10 LCD M549SS...
Страница 57: ...Part Lists DVD Dual Drive A 13 A Part Lists DVD Dual Drive Figure A 11 DVD Dual Drive...
Страница 58: ...Part Lists A 14 A Part Lists...