1-26 Cisco 7010 Hardware Installation and Maintenance
Physical Description
Figure 1-16
Fast Ethernet Interface Processor
Following are the product numbers associated with the FEIP:
•
CX-FEIP-1TX= (interface processor with one 100BaseTX port adapter)
•
CX–FEIP-2TX= (interface processor with two 100BaseTX port adapters)
The interfaces on an FEIP can both be configured at 100 Mbps, half duplex (HDX) or full duplex
(FDX), for a maximum aggregate bandwidth of 200 Mbps. The FEIP microcode boot image resides
in an EPROM in socket location U37.
For maximum port densities, refer to the section “Port Densities” in this chapter.
Fiber Distributed Data Interface Processor (FIP)
The FIP contains a 16-mips processor for high-speed (100 Mbps) interface rates and the
industry-standard AMD SuperNet chipset for interoperability. Figure 1-17 shows a
multimode/multimode FIP on the bottom and a single-mode/multimode FIP on the top. The FIP
supports single-attach stations (SASs), dual-attach stations (DASs), dual homing, and optical
bypass. The FIP complies with ANSI X3.1 and ISO 9314 FDDI standards. The default FIP
microcode resides on a ROM in socket U23.
Figure 1-17
FDDI Interface Processor (FIP), Multimode/Multimode and
Single-Mode/Multimode
H2940
DRAM
SIMMs
Microcode
ROM U37
Bus connector
MII
RJ-45
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Страница 258: ...A 16 Cisco 7010 Hardware Installation and Maintenance MIP Interface Cable Pinouts ...
Страница 270: ...B 12 Cisco 7010 Hardware Installation and Maintenance Interface Processor LEDs ...
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