VCC-G20S20A
Rev.900-651-33-00
©2010 CIS Corporation. All rights reserved.
7
4.2. Camera Output Signal Specification
Video output
Effective output
1360(H)
×
1040(V)
at full frame scan mode
Sync signals
Input /Output
HD/VD Input signal level:
2
～
5Vp-p
Input impedance:
10k
Ω
75
Ω
can be set as optional factory
setting.
Allowable frequency deviation:
±
3%
Phase difference:
HD/VD: under 0±5
μ
s
Jitter: under
20ns
(Referential Drawing)
HD/VD/WEN output
CMOS (74VHC04 equivalent)
Output impedance:
100
Ω
HD/VD/WEN output signal level
Low 0.5V (Max), High 4V (Min)
Trigger input
Polarity:
Positive
Input signal level:
Low 0.5V (Max), High 2.5
～
5V
Input impedance:
1k
Ω
Trigger input width: 4
μ
s
～
250ms
(Referential Drawing)
Scan IN input
Scan switching at
No.9 pin.
Input signal level: Low 0.5V (Max), High 2.5
～
5V
Input impedance: 10k
Ω
(Pull Up)
(Referential Drawing)
Video signals
VS output 1.0V (p-p), Sync. Negative, 75
Ω
unbalanced, DC connect
White clip level:
840 ± 70 mVp-p
Setup level:
25 ± 15 mVp-p (Gain 0dB)
SYNC level:
290 ± 50 mVp-p
VS DC level:
0 ± 100 mV
